Senior DDR5/DDR6 Analog Lead for SoC Memory

Renesas Electronics Corp.; Johns Creek (GA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Competitive benefits

Diversity & Inclusion

Job summary

Renesas Electronics Corp. in Johns Creek, GA, seeks a Senior Analog Engineering Manager to lead DDR5/DDR6 PHY development for next‑gen SoCs.

You will guide architecture, design, and end‑to‑end delivery of high‑performance, low‑power memory interfaces and own cross‑functional program execution. You will build and mentor a team of analog/mixed‑signal designers, drive post‑silicon bring‑up, debug, and yield improvements, and shape the DDR6 roadmap while ensuring JEDEC DDR5/DDR6 alignment and

Qualifications

• Bachelor’s or Master’s in Electrical Engineering; PhD preferred.
• 12+ years in analog/mixed-signal IC design with deep focus on high-speed memory interfaces.
• 5+ years of people-management and technical leadership experience.
• Proven hands-on delivery of DDR5 PHYs or late-stage DDR4 designs transitioning to DDR5.
• Strong expertise in high-speed IO design, PLL/DLL, signal integrity, and CMOS IO design.

Responsibilities

• Lead architecture, design, and implementation of DDR5 PHYs; contribute to DDR6-ready architectures.
• Oversee post-silicon bring-up, characterization, debugging, and yield improvements.
• Provide technical oversight for analog and mixed-signal blocks, including TX/RX datapaths and timing closure.
• Build and mentor a team of analog/mixed-signal designers and set performance expectations.
• Collaborate with SoC teams, packaging, PCB, SI/PI, validation, product, and management.

Skills

High-speed IO design

Memory interface design

Technical leadership

DDR5/DDR6 knowledge

Clocking architectures

Silicon bring-up

Project ownership

Cross-functional collaboration

Education

Bachelor’s or Master’s in Electrical Engineering, PhD preferred

Tools

DDR5 DDR6 design tools

Job description

Renesas Electronics Corp. in Johns Creek, GA, seeks a Senior Analog Engineering Manager to lead DDR5/DDR6 PHY development for next‑gen SoCs.

You will guide architecture, design, and end‑to‑end delivery of high‑performance, low‑power memory interfaces and own cross‑functional program execution. You will build and mentor a team of analog/mixed‑signal designers, drive post‑silicon bring‑up, debug, and yield improvements, and shape the DDR6 roadmap while ensuring JEDEC DDR5/DDR6 alignment and