Principal Formal Verification Engineer (CPU)

NUVACORE; Santa Clara (CA); Presencial; USD 140.000 - 210.000; Jornada completa

Descripción de la vacante

NUVACORE is building a high-performance, low-power CPU and seeks Formal Verification Engineers from Senior to Principal levels to prove correctness with formal methods. You will convert micro-architecture specs into properties, build formal environments, and drive proofs using model checking and equivalence checking.

As part of the DV team, you will collaborate with design engineers to chase deep bugs, establish coverage, and automate flows with Python/TCL.

Formación

• Degree in Electrical/Computer Engineering, Computer Science, or Mathematics, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, with hands-on formal verification.
• Hands-on formal techniques — model checking and/or equivalence checking — through to proof convergence.
• Strong Verilog/SystemVerilog and assertions / temporal logic.
• Strong knowledge of CPU micro-architecture and digital logic.
• Strong scripting (Python; TCL/Perl a plus), analytical, and debug skills.

Responsabilidades

• Plan & Strategy: Drive the verification scope and formal test plan for each verification problem, turning the micro-architecture specification into the properties to prove.
• Formal Environment: Build the formal environment — assumptions, constraints, assertions, and cover properties — plus reusable, optimized formal models.
• Proof & Bug Hunting: Apply model checking, equivalence checking, and abstraction to reach full or bounded proofs, and hunt deep bugs in areas such as cache coherence, memory consistency, and speculative execution.
• Debug & Design Feedback: Debug counterexamples to root cause and partner directly with designers to fix and improve the micro-architecture.
• Flow & Automation: Build and maintain the end-to-end formal flow — automation (Python/TCL), assertion libraries shared across formal and simulation, and tool-issue resolution with vendors.
• Cross-functional Collaboration: Review formal setups and proofs with the design team, and partner closely across the DV team.

Conocimientos

Formal verification

Model checking

Equivalence checking

Verilog / SystemVerilog

Python scripting

TCL/Perl scripting

Debugging

Educación

Bachelor's degree in EE/CS/Math

Herramientas

Cadence JasperGold

Synopsys VC Formal

Siemens Questa Formal

Descripción del empleo

NUVACORE is building a high-performance, low-power CPU and seeks Formal Verification Engineers from Senior to Principal levels to prove correctness with formal methods. You will convert micro-architecture specs into properties, build formal environments, and drive proofs using model checking and equivalence checking.

As part of the DV team, you will collaborate with design engineers to chase deep bugs, establish coverage, and automate flows with Python/TCL.