Senior CPU Performance Architect – Microarchitecture Lead

NVIDIA Corporation; Santa Clara (CA); On-site; USD 272,000 - 431,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA in Santa Clara, CA is seeking a Senior CPU Performance Architect to push microarchitectural boundaries and advance CPU performance across modern cores, systems, and accelerators. You will model improvements, evaluate their feasibility, and collaborate with build, verification and post-silicon teams to deliver reliable, power-efficient designs.

Lead microarchitectural initiatives, communicate tradeoffs, and partner with senior architects to meet timing, area and power targets.

Qualifications

• Deep understanding of brand new CPU microarchitecture and architecture.
• Proven track record of CPU microarchitectural innovation across Front End, Midcore, and Memory Subsystem.
• Experience in performance modeling, debugging, and demonstrating merit of ideas.
• Strong collaboration with build and verification teams to implement improvements.

Responsibilities

• Innovating and improving CPU performance through modern microarchitectural ideas.
• Modeling potential improvements to determine merit and feasibility.
• Implementing effective solutions and collaborating with build, verification, and post-silicon teams.
• Resolving critical issues related to timing, power, and area to achieve flawless implementation.
• Partnering with lead microarchitects to meet CPU core performance, area, and power targets.
• Advocating for microarchitectural ideas and communicating benefits and drawbacks.

Skills

CPU microarchitecture

Performance modeling

Collaboration

Communication

Advocacy

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Job description

NVIDIA in Santa Clara, CA is seeking a Senior CPU Performance Architect to push microarchitectural boundaries and advance CPU performance across modern cores, systems, and accelerators. You will model improvements, evaluate their feasibility, and collaborate with build, verification and post-silicon teams to deliver reliable, power-efficient designs.

Lead microarchitectural initiatives, communicate tradeoffs, and partner with senior architects to meet timing, area and power targets.