Senior CMP Process Engineer: Planarization & Yield Expert

Samsung; Taylor (TX); On-site; USD 106,000 - 145,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Life insurance and 401(k) matching

Onsite café(s) and workout facilities

Paid maternity and paternity leave

PTO and holidays

Job summary

Samsung Austin Semiconductor in Austin, TX is seeking a CMP Process Engineer to lead planarization of wafer surfaces, controlling chemical reactions and mechanical forces to achieve ultra-flat wafers for subsequent steps. The role partners with process and equipment teams to optimize recipes, monitor performance, and ensure consistency across the wafer.

You will apply SPC and fault analysis, work with CMP tools from major vendors, and adapt to off-hours or shift needs.

Qualifications

• Basic CMP knowledge including slurry-pad-conditioning and post-clean steps.
• Hands-on experience with CMP tools and end point systems (AMAT/EBara).
• Proficiency with SPC, FDC, and analysis software (JMP/Spotfire).
• Ability to drive root-cause analysis using FMEA, 8D, and first-principles.
• Willingness to work off-hours or with varied shift schedules as needed.

Responsibilities

• Removal Rate control: evaluate factors to ensure uniform thickness across wafer.
• Condition optimization to improve uniformity and resolve issues like center low RR.
• Recipe management: develop and optimize RCP parameters for flatness.
• Defect & uniformity: manage defects and improve wafer quality.
• Consumable lifecycle: monitor pads/slurry usage to stay within specs.
• Material evaluation: assess slurries and polishing pads for CMP output.

Skills

CMP knowledge

Equipment familiarity

Data & statistics

Problem solving

Flexibility

Job description

Samsung Austin Semiconductor in Austin, TX is seeking a CMP Process Engineer to lead planarization of wafer surfaces, controlling chemical reactions and mechanical forces to achieve ultra-flat wafers for subsequent steps. The role partners with process and equipment teams to optimize recipes, monitor performance, and ensure consistency across the wafer.

You will apply SPC and fault analysis, work with CMP tools from major vendors, and adapt to off-hours or shift needs.