Senior Circuit Design Engineer — Lead Digital & Mixed-Signal IP

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 168,000 - 265,000; Full time

Benefits offered by this job

Equity

Hybrid work model

Job summary

NVIDIA is seeking a motivated Senior Circuit Design Engineer to join our team in Santa Clara. You will work on deep submicron processor designs, collaborating with global teams to improve netlist timing and noise performance across silicon.

The role requires a BSEE or equivalent with 8+ years, experience with analog/mixed-signal, SPICE simulations, and timing analysis. We offer equity and a hybrid work arrangement, with a base salary range and opportunities across product lines.

Qualifications

• BSEE (or equivalent); MS preferred; 8+ years of circuit design experience.
• Strong understanding of deep submicron process issues and digital circuit design.
• Experience with analog/mixed-signal blocks (op-amp, ADC, etc.).
• Hands-on Spice simulations, EM/IR analysis, and static timing analysis.
• Experience with noise analysis and loop stability analysis.

Responsibilities

• Participate in cutting edge Processor design in deep submicron technologies.
• Design digital, semi-custom and mixed-signal analog circuits for silicon correlation and noise mitigation.
• Collaborate with cross-functional teams to improve performance and reliability of NVIDIA’s next generation products.
• Drive the design and physical implementation of digital and/or mixed-signal IPs for voltage and noise sensing.
• Create prototypes of patentable ideas on test chips and drive deployment across product lines.
• Be a mentor/technical lead for junior team members.

Skills

Deep submicron process

Digital circuit design

Mixed-signal design

Spice simulations

Timing analysis

Mentoring/leadership

Education

BSEE or equivalent

MS in Electrical/Computer Engineering

Tools

Spice simulations

EM/IR analysis

Static timing analysis (STA)

Job description

NVIDIA is seeking a motivated Senior Circuit Design Engineer to join our team in Santa Clara. You will work on deep submicron processor designs, collaborating with global teams to improve netlist timing and noise performance across silicon.

The role requires a BSEE or equivalent with 8+ years, experience with analog/mixed-signal, SPICE simulations, and timing analysis. We offer equity and a hybrid work arrangement, with a base salary range and opportunities across product lines.