Senior Analog & Mixed-Signal Engineer — Equity Eligible

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an experienced design engineer to work on high-speed interfaces and mixed-signal circuits in deep-submicron CMOS. You will contribute to architecture and transistor-level design of PLLs, data converters, and related blocks, collaborating with mask design and silicon-evaluation teams.

The role requires strong analytical skills, hands-on analog/digital design expertise, and proficiency with Cadence ADE tools. Equity and benefits accompany a competitive base salary.

Qualifications

• BSEE or equivalent experience; MS preferred.
• 6+ years in deep-submicron CMOS technologies with transistor-level analog design, layout and simulation.
• Hands-on analog/digital converter and PLL design experience including VCO, LDO, bandgap, charge-pump, opamps.
• Experience with digital PLLs, TDC, DSP and control theory related to PLLs a plus.
• Proficient with Cadence ADE tools and scripting (Perl, Python, MATLAB).
• Ability to run Monte-Carlo, noise simulations and stability analysis.

Responsibilities

• Design and implement high-speed interfaces and complex mixed-signal circuits in sub-micron CMOS.
• Design high-speed analog and hybrid PLLs and related blocks (VCO, charge-pump, dividers, LDO, bandgap).
• Design data converters (ADC/DAC) and blocks like comparators and op-amps.
• Collaborate with mask design engineers for physical design and silicon eval.
• Support technology transfer to product teams.
• Engage in architecture studies, floor-planning, and reliability verifications.
• Learn and adopt new technologies with strong analytical skills.

Skills

High-speed design

Analog circuits

PLL design

Data converters

Analytical thinking

Education

BSEE or equivalent (MS preferred)

Tools

Spectre

HSPICE

AFS

MATLAB

SystemVerilog

Python

Cadence ADE-L

Cadence ADE-XL

Calibre

ICV

Job description

NVIDIA is seeking an experienced design engineer to work on high-speed interfaces and mixed-signal circuits in deep-submicron CMOS. You will contribute to architecture and transistor-level design of PLLs, data converters, and related blocks, collaborating with mask design and silicon-evaluation teams.

The role requires strong analytical skills, hands-on analog/digital design expertise, and proficiency with Cadence ADE tools. Equity and benefits accompany a competitive base salary.