Custom SOC IP Verification Engineer

Jobtailor; California (MO); On-site; USD 168,000 - 264,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify next-generation SOC and IP solutions. This role focuses on verifying cache protocol compliance and ensuring coherency across CPU and GPU memory subsystems in high-performance ASIC designs.

The ideal candidate will have a B.S. or M.S. degree in Computer Engineering or related field and 8+ years of ASIC verification experience, especially in cache coherency protocols. Proficiency in System Verilog, UVM, and AMBA protocols is essential for this position.

Qualifications

• 8+ years of experience in ASIC verification.
• Strong knowledge of cache coherency and memory subsystem verification.
• Experience with AMBA protocols and System Verilog.

Responsibilities

• Verify ASIC design for various processing blocks focusing on cache coherency.
• Develop and complete test plans for cache verification.
• Collaborate with multiple teams for verification plans.

Skills

System Verilog

UVM methodology

ASIC verification

cache coherency protocols

AMBA protocols (AXI, ACE, CHI)

scripting languages (Python, Perl, TCL)

C/C++

Education

B.S. or M.S. degree in Computer Engineering/Electrical Engineering

Job description

NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions! We are looking for special individuals with desire to deliver innovative products. Together, we will build the next generation of life changing custom SOCs! If you are a motivated individual that understands how complex SOC and IPs are built, has intimate knowledge of client requirements, and understand various development cycles, this is your place to be.

This role specifically requires a skilled ASIC Verification Engineer with expertise in cache coherency protocols and AMBA-based interconnects (AXI, ACE, CHI). You will play a key role in verifying the cache protocol compliance and ensuring coherency across CPU and GPU memory subsystems, ensuring that coherency is maintained across complex memory hierarchies in high-performance ASIC designs. This position demands a motivated individual who understands how complex SOCs, and IPs are built, has intimate knowledge of client requirements, and comprehends various development cycles. It requires deep knowledge of System Verilog, UVM, and C++, along with a solid grasp of ASIC verification methodologies.

What you’ll be doing:

• Responsible for ASIC design verification for various processing blocks within a SOC, with a strong focus on cache coherency protocols and complex memory hierarchies.
• Develop and complete test plans for cache coherency verification of ASIC-based SoCs using UVM-based environments.
• Design and implement constrained-random and directed System Verilog testbenches targeting multi-level cache hierarchies and interconnect fabric.
• Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation, and Post-Silicon Validation teams to ensure comprehensive first-time right verification plans and execution.
• Drive the development of silicon and platform verification strategies and methodologies.

What we need to see:

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).
• 8+ years of experience in ASIC verification, particularly in cache coherency or memory subsystem verification.
• Strong knowledge of System Verilog and UVM methodology.
• Hands-on experience with AMBA protocols, especially AXI, ACE, and CHI, demonstrating a strong background with AMBA protocols such as AXI, CHI, ATB, etc.
• Familiarity with SoC architectures, memory models, and CPU-cache interactions.
• Proficiency in scripting languages (Python, Perl, TCL) and working knowledge of C/C++ for testbench or model integration.

Ways to stand out from the crowd:

• Experience with formal verification or assertion-based verification (SVA).
• Knowledge of RISC-V or ARM architecture and system-level cache subsystems.
• Exposure to coherency modeling tools, verification IPs, or emulation platforms (e.g., Palladium, Veloce).
• Experience in GPU-based verification is desirable.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until February 23, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.