Senior ASIC Verification Engineer — Memory Unit, Equity

NVIDIA AI; Alabama; On-site; USD 168,000 - 311,000; Full time

Job summary

NVIDIA is seeking a Senior Verification Engineer to verify the Memory Management Unit for GPUs. You will join a world‑class ASIC verification team, collaborating with architects, designers and software engineers across sites to define verification scope, build testbenches, BFMs, checkers and monitors, and drive coverage.

The role requires 8+ years in ASIC verification, a degree in EE/CS/CE, strong SystemVerilog and C/C++, and experience with VCS/IES and debugging tools like Debussy and GDB.

Qualifications

• Bachelor's or Master's degree in EE/CS/CE or equivalent experience.
• 8+ years of relevant work or research experience.
• Exposure to Computer Architecture, ASIC design and verification methodology.
• Strong SystemVerilog, C/C++, test planning and coverage closure.
• Knowledgeable in constrained random testing with functional coverage and assertions.
• Understanding of object oriented programming concepts.
• Experience with simulation and debugging tools (VCS, IES, Debussy, GDB).
• Strong interpersonal skills and problem solving ability.

Responsibilities

• Understand design and implementation of Memory Management Unit and define verification scope.
• Develop verification infrastructure: testbenches, BFMs, checkers and monitors.
• Implement test/coverage plans and verify design correctness, collaborating across sites.

Skills

SystemVerilog

C/C++

Test planning

Coverage closure

Assertion-based verification

Constrained random testing

Object-oriented programming

Debugging

Interpersonal skills

Education

Bachelor's degree in Electrical Engineering or Computer Science or Computer Engineering

Master's degree in Electrical Engineering or Computer Science or Computer Engineering

Tools

VCS

IES

Debussy

GDB

Job description

NVIDIA is seeking a Senior Verification Engineer to verify the Memory Management Unit for GPUs. You will join a world‑class ASIC verification team, collaborating with architects, designers and software engineers across sites to define verification scope, build testbenches, BFMs, checkers and monitors, and drive coverage.

The role requires 8+ years in ASIC verification, a degree in EE/CS/CE, strong SystemVerilog and C/C++, and experience with VCS/IES and debugging tools like Debussy and GDB.