Senior ASIC Verification Engineer — Space-Grade UVM

BLUE ORIGIN; San Francisco (CA); On-site; USD 197,529 - 276,539; Full time

Benefits offered by this job

Medical, dental, vision insurance

Paid parental leave

401(k) with company match

Job summary

BLUE ORIGIN is seeking an experienced engineer to lead verification efforts in San Francisco. The role involves developing and executing verification plans, creating UVM environments, and mentoring junior engineers. Applicants should have a strong background in System Verilog and ASIC verification, with 5-8+ years of experience required. Competitive compensation and comprehensive benefits including medical, dental, and a 401(k) plan are offered.

Qualifications

• 5–8+ years of ASIC/SoC verification experience.
• Deep hands‑on expertise in System Verilog and UVM.
• Strong understanding of verification planning, assertions, and coverage closure.

Responsibilities

• Lead verification planning and execution for complex blocks or subsystems.
• Develop sophisticated UVM environments and verification strategies.
• Mentor junior engineers in verification standard processes.

Skills

System Verilog

UVM

ASIC/SoC verification

Debugging

Collaboration

Education

BS or MS in Electrical Engineering, Computer Engineering, or related field

Job description

BLUE ORIGIN is seeking an experienced engineer to lead verification efforts in San Francisco. The role involves developing and executing verification plans, creating UVM environments, and mentoring junior engineers. Applicants should have a strong background in System Verilog and ASIC verification, with 5-8+ years of experience required. Competitive compensation and comprehensive benefits including medical, dental, and a 401(k) plan are offered.