Senior ASIC Verification Engineer - Clocking & Systems

NVIDIA AI; Santa Clara (CA); On-site; USD 116,000 - 218,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA's Clocks team is looking for an experienced ASIC Design Verification engineer to join our group and ensure high-quality clocking and reset logic across SOC and GPU ASICs. You will lead verification efforts from planning to productization, using SystemVerilog, UVM, C++, Python, and NVIDIA tools.

Work closely with clocks architecture/design teams to validate complex clocking designs, coordinate with teams across time zones, and leverage advanced verification methodologies to deliver

Qualifications

• BS or MS in EE/ECE or equivalent experience.
• 3+ years of proven design verification experience.
• Strong understanding of Logic Design and Architecture.
• Expertise in verification flows like SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop.

Responsibilities

• Own validation of Clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
• Tackle sophisticated problems and develop scalable solutions across platforms.
• Hands-on with System Verilog, UVM, C++, Perl, Python, and NVIDIA tools.
• Coordinate with clocks architecture and design teams to validate clock designs.
• Collaborate with internal and external teams across time zones.

Skills

SystemVerilog

UVM

C++

Python

Perl

Formal Verification

Coverage Metrics

X prop

Education

BS or MS in EE/ECE or equivalent

Job description

NVIDIA's Clocks team is looking for an experienced ASIC Design Verification engineer to join our group and ensure high-quality clocking and reset logic across SOC and GPU ASICs. You will lead verification efforts from planning to productization, using SystemVerilog, UVM, C++, Python, and NVIDIA tools.

Work closely with clocks architecture/design teams to validate complex clocking designs, coordinate with teams across time zones, and leverage advanced verification methodologies to deliver