Senior ASIC Validation Engineer - PCIe/NVMe Expert

Microchip Technology Inc.; Basking Ridge (NJ); On-site; USD 70,000 - 140,000; Full time

Benefits offered by this job

Health benefits starting day one

Retirement savings plans

ESPP program with 2 year look back

Job summary

Microchip Technology Inc. in the United States is seeking a senior engineer for pre- and post-silicon validation of NVMe flash controllers, focusing on PCIe, NVMe protocols, and embedded low-level programming with JTAG.

You will work within a cross-functional team, developing validation plans, building drivers and test tools in C, Python, and Tcl, and influencing future product architecture through hands-on debugging and performance analysis.

Qualifications

• Bachelor or Master degree in CS, CE, EE.
• 5+ years for Senior I
• Proficient in Tcl and Python scripting.
• Strong C and/or embedded C programming.
• Excellent knowledge of digital systems and computer architecture.
• Ability to develop functional validation plans and software to execute them.
• Excellent verbal and written communication skills.

Responsibilities

• Plan, develop, code, and execute pre‑silicon and post‑silicon validation plans.
• Operating System level debug of post‑silicon hardware and software issues.
• Analysis and debug of PCIe and NVMe protocols.
• Build and support validation infrastructure through embedded software, device drivers, and test tools in C, Python, Tcl.

Skills

C programming

Embedded C

Python

Tcl

Digital systems

Computer architecture

Education

Bachelor's or Master's in CS/EE/CE

Tools

Protocol analyzers

Windows/Linux device drivers

Lab equipment

Job description

Microchip Technology Inc. in the United States is seeking a senior engineer for pre- and post-silicon validation of NVMe flash controllers, focusing on PCIe, NVMe protocols, and embedded low-level programming with JTAG.

You will work within a cross-functional team, developing validation plans, building drivers and test tools in C, Python, and Tcl, and influencing future product architecture through hands-on debugging and performance analysis.