Senior ASIC Validation Engineer - AI Accelerators

Amazon; Cupertino (CA); On-site; USD 183,000 - 248,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino, CA is seeking a Sr ASIC validation engineer to lead SW-driven test development for Trainium and Inferentia engines, directing pre-silicon verification and ensuring silicon quality.

You will mentor engineers, collaborate across architects, design, verification, and software teams, and influence technical investments while shaping validation strategies for multiple chip generations.

Qualifications

• 6+ years of verification or chip design experience.
• 2+ years HW/SW co-design-based testing.
• 3+ years validation of AI acceleration engines.
• Knowledge of AI acceleration HW architecture.
• Understanding of verification methodologies and coverage.

Responsibilities

• Develop, run and debug SW based testing primarily for pre-silicon validation of compute and AI acceleration engines.
• Develop unit and end-to-end testing across single engines and neural network layers.
• Focus on early development of testing and quick ramp of Neuron testing on emulation.
• Contribute and debug across RTL through firmware, software and testbench development.
• Reuse and scale verification infra across pre-Si and emulation teams.
• Collaborate with Architects, Chip design, chip verification, post silicon validation and software teams.
• Drive strategic technical decisions across verification teams and product lines.

Skills

HW/SW co-design testing

ML accelerator testing

Emulation testing

Computer architecture

Education

Masters in computer Science or Electrical Engineering

Tools

Emulation platforms

RTL

Firmware

Job description

Annapurna Labs (U.S.) Inc. in Cupertino, CA is seeking a Sr ASIC validation engineer to lead SW-driven test development for Trainium and Inferentia engines, directing pre-silicon verification and ensuring silicon quality.

You will mentor engineers, collaborate across architects, design, verification, and software teams, and influence technical investments while shaping validation strategies for multiple chip generations.