Senior ASIC/SoC Verification Engineer - Impactful Role

Experis-US; San Jose (CA); On-site; USD 138,000 - 141,000; Full time

Benefits offered by this job

Medical and Prescription Drug Plans

Dental Plan

Vision Plan

Health Savings Account

Health Flexible Spending Account

Dependent Care Flexible Spending Allow

Supplemental Life Insurance

Short Term and Long Term Disability保险

Business Travel Insurance

401(k) Plus Match

Weekly Pay

Job summary

Experis Technology Group, on behalf of a premier semiconductor and hardware company in San Jose, seeks a Verification Engineer 5 to join the Verification Department. You will contribute to ASIC/SoC verification, design test plans, and run constrained-random tests in simulation.

The role requires 10+ years in large ASIC projects, strong C/C++ in Linux, and proficiency with Verilog, SystemVerilog, SystemC, DPI/PLI.

Qualifications

• 10+ years of verification experience on large ASIC development projects.
• Strong C/C++ development in a Linux environment.
• Proficiency with debug tools such as GDB and Valgrind.
• Knowledge of Verilog, SystemVerilog, SystemC; DPI/PLI in C/Verilog environments preferred.
• Excellent collaboration and communication skills.

Responsibilities

• Participate in the functional verification of complex ASIC blocks and IP cores.
• Collaborate with design and verification engineers to verify design functionality within system context.
• Develop and execute detailed test plans, including directed and constrained-random tests during simulation.
• Adopt and implement evolving verification methodologies to verify increasingly complex SoC designs.

Skills

Analytical thinking

Strong communication

Collaborative mindset

Debugging

Tools

GDB

Valgrind

Verilog

SystemVerilog

SystemC

DPI/PLI

Job description

Experis Technology Group, on behalf of a premier semiconductor and hardware company in San Jose, seeks a Verification Engineer 5 to join the Verification Department. You will contribute to ASIC/SoC verification, design test plans, and run constrained-random tests in simulation.

The role requires 10+ years in large ASIC projects, strong C/C++ in Linux, and proficiency with Verilog, SystemVerilog, SystemC, DPI/PLI.