Senior ASIC Power Architect – Wireless SOC (Low Power)

Apple, Inc.; Sunnyvale (CA); On-site; USD 185,000 - 325,000; Full time

Job summary

Apple Inc. is seeking a senior role in its wireless silicon development team focused on low power architecture, power modeling and correlation. You will define power-efficient SOC architecture, build models and collect pre-silicon data to drive energy efficiency for billions of devices.

The position requires strong ASIC power knowledge, scripting skills and experience with low power techniques. Location is Sunnyvale, CA, with competitive compensation and benefits.

Qualifications

• BS and a minimum of 10 years relevant industry experience.
• ASIC power knowledge required.
• Experience with power tools such as Power PX and Power Artist.
• Understanding of ASIC logic design and low power techniques (UPF).
• Proficiency in scripting languages (Shell, Perl or Python).

Responsibilities

• Define power efficient SOC architecture and schemes, write power spec.
• Build wireless application and atomic power model with high accuracy.
• Define and generate power vectors with Design and DV support.
• Collect pre-silicon power data using power flow and tools.
• Analyze and identify power reductions.
• Support post-silicon power correlation.

Skills

ASIC power knowledge

Scripting languages

Understand ASIC logic design

Low power design & UPF

Power modeling experience

Education

Bachelor's degree in engineering or related field

Tools

Power PX

Power Artist

Job description

Apple Inc. is seeking a senior role in its wireless silicon development team focused on low power architecture, power modeling and correlation. You will define power-efficient SOC architecture, build models and collect pre-silicon data to drive energy efficiency for billions of devices.

The position requires strong ASIC power knowledge, scripting skills and experience with low power techniques. Location is Sunnyvale, CA, with competitive compensation and benefits.