Senior ASIC Physical Verification Engineer

Amazon Web Services (AWS); Austin (TX); On-site; USD 159,000 - 215,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Austin, Texas is seeking an ASIC Physical Design Integration and Verification Engineer to ensure quality and manufacturability of complex semiconductor designs through physical verification.

You will drive full chip floorplanning, sign-off, and implement robust verification methodologies. The role requires strong scripting, extensive back-end design experience, and collaboration with layout teams.

Qualifications

• BS + 10yrs or MS + 7yrs in EE/CS, or related field
• 5+ in physical verification for advanced technology nodes
• Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS)
• Strong communication and collaboration abilities
• Design Flow Knowledge: Understanding of backend physical design flows (FC/Innovus)
• Proven track record of successful tape-outs

Responsibilities

• Drive full chip floorplan, integration and physical verification sign-off and closure
• Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (Calibre, IC Validator)
• Perform DRC, LVS, PERC verification, and Fill insertion
• Debug and resolve physical verification issues in collaboration with layout and design teams
• Interface with foundries for MT form, rule deck updates and violation waivers
• Develop and maintain verification runsets and methodologies
• Support technology file development and qualification
• Fine tune cloud infrastructure to improve compute and storage utilization for physical design work
• Mentor junior engineers on physical verification methodologies and closure

Skills

Python

Perl

Scripting language

Strong communication

Tape-outs

Education

BS + 10yrs or MS + 7yrs in EE/CS

Tools

Calibre

IC Validator

PVS

FC/Innovus

Job description

Annapurna Labs (U.S.) Inc. in Austin, Texas is seeking an ASIC Physical Design Integration and Verification Engineer to ensure quality and manufacturability of complex semiconductor designs through physical verification.

You will drive full chip floorplanning, sign-off, and implement robust verification methodologies. The role requires strong scripting, extensive back-end design experience, and collaboration with layout teams.