Sr. Physical Design Verification Engineer, Annapurna Labs

Amazon; Cupertino (CA); On-site; USD 190,000 - 240,000; Full time

Job summary

Amazon's Annapurna Labs seeks a Sr. Physical Design Verification Engineer to lead full chip verification efforts and collaborate with layout teams in Cupertino/Austin. You will drive methodologies, tape-out readiness, and mentorship, shaping cloud silicon excellence.

The role requires deep scripting, backend flow experience, and a proven record of successful tape-outs on advanced nodes. Strong cross-team communication is essential in a fast-paced environment.

Qualifications

• Experience with Python/Perl or similar scripting language.
• BS + 10 yrs or MS + 7 yrs in EE/CS or related field.
• 5+ years in physical verification for advanced tech nodes.
• Expert knowledge of Calibre, IC Validator, and PVS.
• Understanding of semiconductor manufacturing and design rules.
• Proven tape-out track record.
• Strong communication and collaboration abilities.
• Design flows knowledge: FC/Innovus backend physical design.

Responsibilities

• Drive full chip floorplan, integration, and physical verification sign-off.
• Define, execute and optimize verification methodologies with Calibre, IC Validator.
• Perform DRC, LVS, PERC verification and fill insertion.
• Debug and resolve physical verification issues with layout/design teams.
• Interface with foundries for MT form updates and violation waivers.
• Develop and maintain verification runsets and methodologies.
• Support technology file development and qualification.
• Mentor junior engineers on verification methodologies and closure.

Skills

Python

Perl

Backend flows

Tape-out experience

Education

BS + 10 yrs or MS + 7 yrs in EE/CS

Tools

Calibre

IC Validator

PVS

Job description

Sr. Physical Design Verification Engineer, Annapurna Labs

Annapurna Labs (our organization within AWS Utility Computing) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

Key Responsibilities

• Drive full chip floorplan, integration, and physical verification sign‑off and closure.
• Define, execute and optimize next‑generation physical verification and integration methodologies using industry‑standard EDA tools (Calibre, IC Validator).
• Perform DRC, LVS, PERC verification, and fill insertion.
• Debug and resolve physical verification issues in collaboration with layout and design teams.
• Interface with foundries for MT form, rule deck updates and violation waivers.
• Develop and maintain verification runsets and methodologies.
• Support technology file development and qualification.
• Fine‑tune cloud infrastructure to improve compute and storage utilization for physical design work.
• Mentor junior engineers on physical verification methodologies and closure.

Basic Qualifications

• Experience in Python, Perl, or another scripting language.
• BS + 10 yrs or MS + 7 yrs in EE/CS, or related field.
• 5+ years in physical verification for advanced technology nodes.
• Expert knowledge of industry‑standard physical verification tools (Calibre, IC Validator, PVS).
• Strong understanding of semiconductor manufacturing processes and design rules.
• Proven track record of successful tape‑outs.
• Strong communication and collaboration abilities.
• Design flow knowledge: understanding of backend physical design flows (FC/Innovus).

Preferred Qualifications

• Experience with integration and verification in advanced nodes (5 nm or below).
• Knowledge of custom and digital design flows.
• Expertise with DFM methodologies.
• Expertise in reliability verification (ESD, EM, IR drop).
• Background in layout design or custom IC development.

Location

• Cupertino, CA
• Austin, TX

Equal Opportunity Employer Statement

Amazon is an equal‑opportunity employer and does not discriminate on the basis of protected veteran status, disability, or other legally protected status.