Senior ASIC Physical Design Engineer Tapeout

Amazon Web Services (AWS); Austin (TX); On-site; USD 159,200 - 215,300; Full time

Job summary

Annapurna Labs (U.S.) Inc. in the United States is seeking an experienced ASIC Physical Design Engineer to design and optimize hardware for AWS data centers, including Inferentia and Trainium systems, with a focus on high-quality tapeouts.

You will lead full-chip floorplanning, placement and PV signoff, collaborating with FE to integrate RTL and push advanced verification methodologies across FC/Innovus flows.

Qualifications

• BS + 10yrs or MS + 7yrs in EE/CS, or related field
• 5+ in physical verification for advanced technology nodes
• Design Flow Knowledge: Understanding of backend physical design flows for chip-top/subsystems (FC/Innovus)
• Expert knowledge of industry-standard physical verification tools (Calibre, IC Validator, PVS)
• Strong understanding of semiconductor manufacturing processes and design rules
• Proven track record of successful tape-outs
• Strong communication and collaboration abilities
• Mentoring, leading, or managing more junior engineers (preferred)

Responsibilities

• Drive full chip floorplan, placement, integration, PV signoff and tapeout
• Collaborate with FE team to understand RTL and drive physical aspects early in design cycle
• Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (FC, Calibre, IC Validator)
• Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification
• Debug and resolve physical verification issues in collaboration with layout and design teams
• Interface with foundries for MT form, rule deck updates and violation waivers; Develop and maintain verification runsets and methodologies
• Mentor junior engineers on physical verification methodologies and closure

Skills

Scripting: Python/Perl/Bash/PowerShell

Physical verification

Backend physical design flows (FC/Is)

Education

BS + 10yrs or MS + 7yrs in EE/CS

Tools

Calibre

IC Validator

PVS

Job description

Annapurna Labs (U.S.) Inc. in the United States is seeking an experienced ASIC Physical Design Engineer to design and optimize hardware for AWS data centers, including Inferentia and Trainium systems, with a focus on high-quality tapeouts.

You will lead full-chip floorplanning, placement and PV signoff, collaborating with FE to integrate RTL and push advanced verification methodologies across FC/Innovus flows.