Innovative ASIC Design Engineer II | RTL & Microarchitecture

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 157,300 - 212,800; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid time off

Parental leave

Job summary

Annapurna Labs (U.S.) Inc. is seeking an ASIC Design Engineer in Cupertino, CA to design and optimize high-performance RTL for AWS data-center SoCs including Inferentia. You will contribute to microarchitectures, SystemVerilog RTL, and post-silicon validation with a team of architects and verification engineers.

Ideal candidates have a strong background in RTL design, power/area trade-offs, and a passion for innovation, accelerated by AWS culture and collaboration across multiple disciplines.

Qualifications

• Bachelor's degree or equivalent.
• 3+ years of non-internship design or architecture experience.
• Master's degree in computer science or equivalent is preferred.

Responsibilities

• Develop high-performance, area and power-efficient RTL designs to meet specs.
• Analyze designs, microarchitectures, and architectures to optimize trade-offs.
• Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs.
• Perform lint and clock domain crossing quality checks.

Skills

Bachelor's degree or equivalent

3+ years design/architecture

SystemVerilog RTL

Education

Bachelor's degree or equivalent

Master's degree in CS or equivalent

Tools

SystemVerilog

RTL design tooling

Job description

Annapurna Labs (U.S.) Inc. is seeking an ASIC Design Engineer in Cupertino, CA to design and optimize high-performance RTL for AWS data-center SoCs including Inferentia. You will contribute to microarchitectures, SystemVerilog RTL, and post-silicon validation with a team of architects and verification engineers.

Ideal candidates have a strong background in RTL design, power/area trade-offs, and a passion for innovation, accelerated by AWS culture and collaboration across multiple disciplines.