Hardware PD Methodology Engineer

Amazon Web Services (AWS); Austin (TX); On-site; USD 136,000 - 184,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a senior ASIC physical design professional to design and optimize hardware in data centers, focusing on high-performance, low-power PD flows and PPA improvements using tools like Innovus and FusionCompiler.

You will collaborate with RTL, Physical Design, DFT and package teams, develop CAD flows, and drive tool evaluations with EDA vendors to push QoR and cost-efficiency.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 3+ years in developing design methodology or CAD flows in synthesis, PNR, or sign-off areas for advanced technology nodes.
• Experience in writing production scripts for implementation and sign-off tools in TCL, Perl, and/or Python.
• Solid understanding of ASIC physical design, physical design flows, and methodologies including synthesis, place and route, STA, formal verification.
• Proven track record of delivering metric driven PPA flow development and support.

Responsibilities

• Create and support innovative physical design methodology and CAD flows.
• Develop cloud infrastructure to support physical design work.
• Drive improvement in RTL2GDS flows/methodology for PPA and TAT improvement.
• Create Dashboard/central reports for project tracking and visualizing QoR/stats
• Interface directly with RTL, Physical Design, Package Design, DFT and other teams to improve methodologies and efficiencies and drive efforts to resolution.
• Work with EDA tool vendors to evaluate new tools, solve bugs, improve usability, etc.

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Innovus

ICC2

FusionCompiler

STA

Sign-Off

Job description

Annapurna Labs (U.S.) Inc. in Austin, TX is seeking a senior ASIC physical design professional to design and optimize hardware in data centers, focusing on high-performance, low-power PD flows and PPA improvements using tools like Innovus and FusionCompiler.

You will collaborate with RTL, Physical Design, DFT and package teams, develop CAD flows, and drive tool evaluations with EDA vendors to push QoR and cost-efficiency.