Senior ASIC Physical Design Engineer - Remote/Onsite

Highbrow Technology Inc; San Jose (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Highbrow Technology Inc is seeking a Senior Physical Design Engineer with 8+ years of hands-on ASIC physical design experience. The role covers floorplanning, placement, CTS, routing, and timing closure, with close collaboration across RTL, STA, DFT, and verification teams.

The ideal candidate has deep expertise in physical design tools (Cadence Innovus), power integrity, STA, and signoff, and can drive flow development for multi-node tape-outs.

Qualifications

• Experience in ASIC/SoC Physical Design and RTL-to-GDSII implementation.
• Hands-on experience with floorplanning, placement, CTS, routing, and timing closure.
• Experience with industry-standard physical design tools such as Cadence Innovus.
• Strong understanding of power planning, power grid design, and physical implementation methodologies.
• Experience with Static Timing Analysis (STA) and timing optimization.
• Hands-on experience with DRC/LVS, LEC, and physical design signoff.
• Experience with clock tree synthesis (CTS) and clock optimization.
• Knowledge of IR drop, electromigration (EM), and power integrity is a plus.
• Experience with hierarchical physical design is a plus.
• Experience with multiple technology nodes and tape-outs is a plus.
• Familiarity with low-power design techniques such as power gating, multi-Vt, and voltage islands is a plus.
• Scripting/programming experience using Tcl, Perl, Python, or similar languages is a plus.
• Experience in physical design flow development, automation, or methodology improvement is a plus.
• Ability to work closely with RTL, STA, DFT, verification, and other cross-functional teams.

Responsibilities

• Lead ASIC/SoC Physical Design from floorplanning through timing closure.
• Perform floorplanning, placement, CTS, routing, and timing closure.
• Collaborate with RTL, STA, DFT, verification, and cross-functional teams.
• Develop and optimize physical design flows and methodologies.
• Sign-off on physical design including GDSII release and signoff.
• Address power integrity issues including IR drop and EM.

Skills

ASIC physical design

Timing closure

RTL to GDSII

Power integrity

Scripting (Tcl/Perl/Python)

Cross-functional collaboration

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Cadence Innovus

Job description

Highbrow Technology Inc is seeking a Senior Physical Design Engineer with 8+ years of hands-on ASIC physical design experience. The role covers floorplanning, placement, CTS, routing, and timing closure, with close collaboration across RTL, STA, DFT, and verification teams.

The ideal candidate has deep expertise in physical design tools (Cadence Innovus), power integrity, STA, and signoff, and can drive flow development for multi-node tape-outs.