Senior ASIC/FPGA Verification Engineer [Onsite]

Anysilicon; Fort Wayne (IN); Hybrid; USD 120,000 - 170,000; Full time

Job summary

Collins Aerospace is seeking a Senior ASIC/FPGA Verification Engineer for the Fort Wayne, IN site. The role focuses on building verification environments using SystemVerilog/UVM, developing testbenches, and guiding the verification effort for ASIC/FPGA integration in defense-grade projects.

Applicants must hold a U.S. government security clearance and be a U.S. citizen. Collaboration with a cross-functional team and mentoring of junior engineers are key aspects of the position.

Qualifications

• Degree in STEM or related field required; advanced degree a plus.
• 5+ years of related experience; security clearance expected.
• Experience in RTL verification environments and testbenches.
• Experience with SystemVerilog/VHDL/Verilog and verification methodologies.

Responsibilities

• Design and architect verification environments using SystemVerilog with OVM/UVM.
• Create test plans and track coverage.
• Develop testbenches for RTL blocks using VHDL/SystemVerilog.
• Collaborate with ASIC/FPGA teams for integration and validation.
• Mentor junior engineers and lead verification efforts.
• Contribute to project estimates and planning.

Skills

SystemVerilog

Verilog

VHDL

UVM

Constrained-random testing

Functional coverage

RTL verification

Git

Subversion

Scripting

Education

Bachelor's degree in STEM or related field

Advanced Degree in related field

Tools

QuestaSim

Synplify

Quartus

Vivado

Git

Subversion

Job description

Collins Aerospace, 1010 Production Road, Fort Wayne, IN 46808

Job Description:

Collins Aerospace, a leader in aerospace and defense technology, is seeking a Senior ASIC/FPGA Verification Engineer to join their Applied Research and Technology Microelectronics Technology team in Fort Wayne, IN. This role involves developing cutting-edge defense solutions and requires an active U.S. government security clearance.

Responsibilities:

• Design and architect verification environments using SystemVerilog with OVM/UVM.
• Create written test plans, test cases, and track code and functional coverage.
• Develop testbenches for RTL block verification using VHDL or SystemVerilog.
• Collaborate with design engineers for ASIC/FPGA integration and validation.
• Mentor junior engineers and provide technical guidance.
• Lead project verification teams by planning activities and reporting status.
• Contribute to engineering estimates for new program pursuits.

Qualifications:

• Bachelor's degree in STEM or related field with 5 years of experience, or an Advanced Degree with 3 years of experience.
• Active U.S. government issued security clearance required prior to start date.
• U.S. citizenship is mandatory for security clearance eligibility.
• Experience in developing and simulating RTL designs using VHDL and/or Verilog.
• Proven ability to design and execute verification testbenches for RTL blocks using VHDL/SystemVerilog.
• Knowledge of chip-level verification methodologies including constrained-random testing and functional coverage.

Skills:

• Proficiency in revision control tools (e.g., Git, Subversion).
• Excellent communication and teamwork skills.
• Experience with high-speed digital interfaces (e.g., DDR, PCIe, Ethernet).
• Familiarity with ASIC/FPGA lab validation and debugging.
• Proficiency in ASIC/FPGA simulation and synthesis tools (e.g., QuestaSim, Synplify, Quartus, Vivado).
• Background in aerospace, defense, or mission-critical systems.
• Proficiency in Unix/Linux environments and scripting.