Senior ASIC/FPGA Design Engineer for Space Comms

Blue Origin; Cupertino, San Diego, Austin (CA, CA, TX); On-site; USD 249,000 - 349,000; Full time

Benefits offered by this job

Medical benefits

Dental benefits

Vision benefits

401(k) with match

Stock options

Job summary

Blue Origin is seeking a Sr ASIC Design Engineer to contribute to the TeraWave program, designing FPGAs and ASICs and leading verification activities. This onsite role is available in Cupertino, CA, with temporary remote work options while sites are developed in San Diego, CA and Austin, TX.

You will collaborate with cross-functional teams to drive timing, congestion, and implementation signoff. Required 7+ years in ASIC design, a BS in Electrical/Computer Engineering, HDL proficiency

Qualifications

• 7+ years of experience in ASIC design and implementation.
• Bachelor's degree in EE/CE or related discipline.
• Proficiency with FPGA & ASIC design.
• HDL programming: VHDL, Verilog, SystemVerilog.
• Experience with Linux development environment.
• Design verification and test bench development experience.

Responsibilities

• Design and develop FPGAs, digital ASICs, and/or mixed-signal ASICs.
• Implement designs using HDL (VHDL, Verilog, SystemVerilog).
• Develop verification methodologies and test benches for block and system-level verification.
• Create and execute test plans, develop test harnesses, and implement coverage models.
• Conduct timing and noise analysis and other signoff checks.
• Collaborate with systems, firmware, architecture, and product engineering.

Skills

ASIC design

FPGA design

HDL (VHDL/Verilog/SV)

Linux development

Verification

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

RTL2GDSII

Job description

Blue Origin is seeking a Sr ASIC Design Engineer to contribute to the TeraWave program, designing FPGAs and ASICs and leading verification activities. This onsite role is available in Cupertino, CA, with temporary remote work options while sites are developed in San Diego, CA and Austin, TX.

You will collaborate with cross-functional teams to drive timing, congestion, and implementation signoff. Required 7+ years in ASIC design, a BS in Electrical/Computer Engineering, HDL proficiency