Senior ASIC Failure Analysis Engineer (Hybrid)

Cisco Systems; San Jose (CA); Hybrid; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems in San Jose, CA is seeking a Failure Analysis Engineer to join the Quality and Reliability group. You will perform failure analysis of ASIC products and work with product test, design, quality, and foundry teams to identify root causes.

The role requires extensive FA experience and knowledge of FA methods. It is a hybrid position with ~3 days in the office in San Jose, offering growth and exposure to advanced semiconductor technologies.

Qualifications

• Bachelor's degree in Electrical/Electronics Engineering (required).
• 8+ years of semiconductor failure analysis experience.
• Experience writing and executing FA plans and interpreting FA results from techniques like cross section, X-ray, CSAM, TDR, FIB, SEM, TEM, IR/EMMI/OBIRCH.
• Validated ability to specify hardware and set up dynamic FA using SIL and LSM.
• Prior experience with fault isolation techniques using ATE, Scan/ATP G, MBIST.

Responsibilities

• Conduct root cause failure analysis of silicon product reliability tests and field failures, proposing corrective actions.
• Develop and implement standard FA processes for all FA equipment.
• Coordinate logistics and instructions to direct the FA process.
• Document and report FA results to management.
• Serve as a technical resource for FA questions.
• Develop and maintain relationships with FA service and equipment vendors.
• Interface with product, test, and design engineering groups to identify and characterize faults on emerging technologies.

Skills

Failure analysis

Root cause analysis

FA techniques

Cross-functional collaboration

FA equipment

Education

Bachelor's degree in Electrical/Electronics Engineering

Master's degree preferred

Tools

X-ray

CSAM

TEM

SEM

FIB

TDR

IR/EMMI/OBIRCH

SIL

LSM

Job description

Cisco Systems in San Jose, CA is seeking a Failure Analysis Engineer to join the Quality and Reliability group. You will perform failure analysis of ASIC products and work with product test, design, quality, and foundry teams to identify root causes.

The role requires extensive FA experience and knowledge of FA methods. It is a hybrid position with ~3 days in the office in San Jose, offering growth and exposure to advanced semiconductor technologies.