Senior ASIC Engineer - Ultra-Low Latency & Tooling Leader

Jane Street Group, LLC; Northern, New York (KY, NY); Hybrid; USD 250,000 - 300,000; Full time

Job summary

Jane Street in the United States (KY) seeks an experienced ASIC Engineer to design, test and deploy advanced hardware for our Ultra Low Latency team, collaborating with trading, networking and research infrastructure.

You will work on both FPGA-based and ASIC-based technologies, leveraging Hardcaml and OCaml tools. Proficiency in Python, C++, Java or Haskell is valued, and base salary ranges from $250,000 to $300,000, with discretionary annual bonus.

Qualifications

• 4+ years practical experience in RTL design and verification.
• ASIC design using Synopsys or Cadence flows; front-end RTL design and synthesis, back-end physical design, or verification (including formal).
• Interest in applying software engineering techniques to hardware; experience in high-level languages (Python, C++, Java, Haskell, etc.).

Responsibilities

• Design, test and deploy advanced hardware designs for an Ultra Low Latency team.
• Collaborate with trading, networking and research infrastructure teams across the firm.
• Work on FPGA-based and ASIC-based technologies and contribute to Hardcaml tooling and OCaml-based workflows.

Skills

RTL design

ASIC design

Verification

Front-end RTL design

Back-end physical design

Formal verification

Python

C++

Java

Haskell

Tools

Synopsys

Cadence

Hardcaml OCaml

OCaml

Job description

Jane Street in the United States (KY) seeks an experienced ASIC Engineer to design, test and deploy advanced hardware for our Ultra Low Latency team, collaborating with trading, networking and research infrastructure.

You will work on both FPGA-based and ASIC-based technologies, leveraging Hardcaml and OCaml tools. Proficiency in Python, C++, Java or Haskell is valued, and base salary ranges from $250,000 to $300,000, with discretionary annual bonus.