ASIC Engineer

Jane Street Group, LLC; Northern, New York (KY, NY); Hybrid; USD 250,000 - 300,000; Full time

Job summary

Jane Street in the United States (KY) seeks an experienced ASIC Engineer to design, test and deploy advanced hardware for our Ultra Low Latency team, collaborating with trading, networking and research infrastructure.

You will work on both FPGA-based and ASIC-based technologies, leveraging Hardcaml and OCaml tools. Proficiency in Python, C++, Java or Haskell is valued, and base salary ranges from $250,000 to $300,000, with discretionary annual bonus.

Qualifications

• 4+ years practical experience in RTL design and verification.
• ASIC design using Synopsys or Cadence flows; front-end RTL design and synthesis, back-end physical design, or verification (including formal).
• Interest in applying software engineering techniques to hardware; experience in high-level languages (Python, C++, Java, Haskell, etc.).

Responsibilities

• Design, test and deploy advanced hardware designs for an Ultra Low Latency team.
• Collaborate with trading, networking and research infrastructure teams across the firm.
• Work on FPGA-based and ASIC-based technologies and contribute to Hardcaml tooling and OCaml-based workflows.

Skills

RTL design

ASIC design

Verification

Front-end RTL design

Back-end physical design

Formal verification

Python

C++

Java

Haskell

Tools

Synopsys

Cadence

Hardcaml OCaml

OCaml

Job description

We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you’ll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.

We’re big believers in the ability of tools to improve the productivity, reliability and day‑to‑day joy of hardware engineering. That’s why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don’t expect you to know OCaml (we’ll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You

• Have 4+ years practical experience in RTL design and verification
• Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following:
  • Front-end RTL design and synthesis
  • Back-end physical design
  • Verification (including formal)
• Interested in using software engineering techniques to improve the hardware design process, and experience programming in some high‑level languages (Python, C++, Java, Haskell, etc.)

Base salary is $250,000 - $300,000. Base salary is only one part of Jane Street total compensation, which includes an annual discretionary bonus.

Jane Street is an Equal Opportunity Employer