Senior ASIC Emulation Engineer

Qualcomm; Austin (TX); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. in Austin, TX seeks an ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement and document IP (block/SoC) for high‑performance, low‑power products.

You will collaborate with software and hardware teams to develop architectures and block designs, using RTL to GDS flows and tools like Virtuoso, emphasizing quality and efficiency.

Qualifications

• 2+ years of ASIC design, verification, validation, integration, or related work.
• 1+ year of ASIC design, verification, validation, integration, or related work with a Master's degree.
• PhD holders meet the listed qualifications.

Responsibilities

• Defines, models, designs (digital/analog), optimizes, verifies, validates, implements and documents IP (block/SoC) development.
• Creates architectures, circuit specs, logic designs, and system simulations from system-level requirements.
• Collaborates with software and hardware teams to meet system requirements and customer needs.
• Assesses design flow from high-level design to placement, routing, timing and power, plus verification.
• Utilizes tools (e.g., RTL to GDS Flow, Virtuoso) to execute architecture and design of IP blocks or ICs.
• Produces detailed technical documentation for EDA/IP/ASIC projects.

Skills

ASIC design

ASIC verification

ASIC validation

ASIC integration

RTL-based design

Verilog/VHDL

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

Virtuoso

RTL to GDS Flow

Python

C/C++

Job description

Qualcomm Technologies, Inc. in Austin, TX seeks an ASIC Engineer to define, model, design (digital and/or analog), optimize, verify, validate, implement and document IP (block/SoC) for high‑performance, low‑power products.

You will collaborate with software and hardware teams to develop architectures and block designs, using RTL to GDS flows and tools like Virtuoso, emphasizing quality and efficiency.