Senior ASIC Design Engineer - XBAR IP

NVIDIA Corporation; United States; Hybrid; USD 120,000 - 150,000; Full time

Job summary

A leading technology firm in the United States seeks a passionate Senior Design Engineer for their Graphics team. This position involves owning micro-architecture and RTL development for advanced memory subsystem components. The ideal candidate has a BS/MS and over 5 years of design experience, particularly in ASIC design flow, and should be proficient in Verilog. The role emphasizes collaboration with various teams, including verification and software, to ensure the success of design features.

Qualifications

• 5+ years of design experience in technology industry.
• Experience in RTL design of complex design units for at least two projects.
• Deep understanding of ASIC design flow.

Responsibilities

• Own micro-architecture and RTL development of design modules.
• Collaborate with verification teams to ensure correctness.
• Interact with FPGA and software teams for design testing.

Skills

RTL design

ASIC design flow

Verilog

Debugging skills

Scripting knowledge

Education

BS / MS in relevant field

Tools

VCS

Debussy

Job description

NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks.**What you’ll be doing:*** Own micro-architecture and RTL development of design modules.* Micro-architect features to meet performance, power and area requirements.* Work with HW architects to define critical features.* Collaborate with verification teams to verify the correctness of implemented features.* Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable.* Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested.* Work on post-silicon verification and debug.**What we need to see:*** BS / MS or equivalent experience.* 5+ years of design experience.* Experience in RTL design of complex design units for at least two or three projects.* Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).* Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug.* Expertise in Verilog.**Ways to stand out from the crowd:*** Design experience in memory subsystem or network interconnect IP.* Good debugging and problem solving skills.* Scripting knowledge (Python/Perl/shell).* Leadership experience in leading small 2-3 member teams.* Good interpersonal skills and ability & desire to work as a part of a team.NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you.We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.#LI-Hybrid