Senior ASIC Design Engineer – AI Networking & DPU

Advanced Micro Devices, Inc.; Santa Clara (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Advanced Micro Devices, Inc. (AMD) is seeking a Senior ASIC Design Engineer in Santa Clara, CA to lead the development of high-speed ASICs for AI networking workloads. The role spans architecture through mass production, requiring deep RTL expertise and strong collaboration with cross-functional teams.

The candidate will architect key blocks, drive verification, and contribute to performance, power, and area optimizations, while working closely with software, hardware, and modeling groups.

Qualifications

• Seasoned ASIC design experience.
• Proven hands-on experience developing high-speed, complex ASICs.
• Strong experience across the complete ASIC development cycle from RTL architecture to tapeout to mass production.
• Solid background in networking and packet-processing architectures.
• Experience collaborating across Verification, Modeling, Software, and Hardware teams.
• Strong RTL design skills in Verilog and SystemVerilog.

Responsibilities

• Architect and design key blocks for next-generation DPU ASICs targeting AI networking workloads.
• Contribute across the full ASIC development lifecycle (architecture, microarchitecture, RTL design, reviews, tapeout, bring-up).
• Collaborate on advanced network processing engines and NoC architectures.
• Design and implement high-speed, complex ASIC blocks for networking and data movement.
• Work with verification, modeling, software, and hardware teams to ensure correctness and performance.
• Produce high-quality design documentation and participate in technical reviews.

Skills

Verilog

SystemVerilog

RTL design

C/C++

Python

Tcl

Education

Bachelor's degree in Electrical Engineering or related

Master's degree preferred

Tools

Synopsys Design Compiler

ModelSim

Job description

Advanced Micro Devices, Inc. (AMD) is seeking a Senior ASIC Design Engineer in Santa Clara, CA to lead the development of high-speed ASICs for AI networking workloads. The role spans architecture through mass production, requiring deep RTL expertise and strong collaboration with cross-functional teams.

The candidate will architect key blocks, drive verification, and contribute to performance, power, and area optimizations, while working closely with software, hardware, and modeling groups.