High-Speed ASIC Analog Layout Engineer

Micron Technology, Inc.; Minneapolis (MN); On-site; USD 74,000 - 127,000; Full time

Job summary

Micron Technology, Inc. in Minneapolis, MN is seeking an ASIC Analog Layout Engineer to drive the physical implementation of high-speed analog and mixed-signal circuits.

You will collaborate with analog designers to optimize performance and manufacturability across SerDes, PLL, DLL, and PHY blocks. Responsibilities include layout development, verification (DRC/LVS/ERC), parasitic optimization, and automation scripting to boost productivity.

Qualifications

• Bachelor's degree in Electrical Engineering or related field, or equivalent industry experience.
• Experience using Cadence Virtuoso or similar custom IC layout tools.
• Experience performing physical verification activities including DRC, LVS, ERC, and antenna rule closure.
• Experience working with semiconductor process technologies and applying analog layout fundamentals to optimize circuit performance and manufacturability.

Responsibilities

• Develop high-quality custom analog and mixed-signal layouts for high-speed ASIC applications.
• Collaborate with analog design engineers to create efficient and manufacturable layout solutions and provide feedback on layout feasibility.
• Perform and debug physical verification checks including LVS, DRC, ERC, and antenna rule analysis.
• Optimize layouts for parasitics, signal integrity, electromigration, ESD robustness, and latch-up prevention.
• Contribute to layout methodologies, hierarchy standards, and process improvements that increase team efficiency.
• Develop automation, scripting, and AI-enabled solutions to improve layout productivity and workflow effectiveness.

Skills

Analog layout

Mixed-signal layout

Custom IC layout

ASIC physical design

IC layout engineering

Scripting (Python/SKILL)

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Cadence Virtuoso

Job description

Micron Technology, Inc. in Minneapolis, MN is seeking an ASIC Analog Layout Engineer to drive the physical implementation of high-speed analog and mixed-signal circuits.

You will collaborate with analog designers to optimize performance and manufacturability across SerDes, PLL, DLL, and PHY blocks. Responsibilities include layout development, verification (DRC/LVS/ERC), parasitic optimization, and automation scripting to boost productivity.