ASIC Analog Layout Engineer

Anysilicon; Minneapolis (MN); On-site; USD 110,000 - 175,000; Full time

Job summary

Micron Technology in Minneapolis seeks an ASIC Analog Layout Engineer to contribute to high-speed analog and mixed-signal blocks for tester and controller IP. You will focus on the physical implementation to ensure performance and reliability across advanced processes.

You will develop custom layouts, collaborate with analog designers, perform LVS/DRC/ERC checks, optimize for parasitics and signal integrity, and contribute automation and AI-enabled tooling to improve productivity.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent.
• Experience with Cadence Virtuoso for analog/mixed-signal layouts.
• Experience with LVS, DRC, ERC, and antenna rule checks.
• Experience with semiconductor process technologies and analog layout fundamentals.
• Master's degree preferred.
• Experience with automation and scripting for layout tasks.

Responsibilities

• Develop high-quality analog and mixed-signal layouts for high-speed ASICs.
• Collaborate with analog design on manufacturable layouts.
• Perform LVS, DRC, ERC, and antenna checks.
• Optimize layouts for parasitics, signal integrity, EM, ESD, latch-up.
• Contribute to layout methodologies and process improvements.
• Develop automation and AI-enabled tooling to improve productivity.
• Troubleshoot layout environment, CAD, and tool issues.
• Support layout for SerDes, PLL, DLL, TX/RX, clocking circuits, and analog front-end.

Skills

Analog layout

Mixed-signal design

ASIC physical design

High-speed circuitry

Python scripting

Parasitic analysis

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Cadence Virtuoso

Quantus Insight

ParagonX

PVL scripting

Job description

Micron, 3001 Broadway Street Northeast, Minneapolis, MN 55413

Job Description:

Micron Technology is seeking an ASIC Analog Layout Engineer to contribute to the development of high-speed analog and mixed-signal circuits for its tester and controller IP. This role focuses on the physical implementation of ASICs, ensuring optimal performance and reliability in advanced semiconductor technologies.

Responsibilities:

• Develop high-quality custom analog and mixed-signal layouts for high-speed ASIC applications.
• Collaborate with analog design engineers to create efficient and manufacturable layout solutions and provide feedback on layout feasibility.
• Perform and debug physical verification checks including LVS, DRC, ERC, and antenna rule analysis.
• Optimize layouts for parasitics, signal integrity, electromigration, ESD robustness, and latch-up prevention.
• Contribute to layout methodologies, hierarchy standards, and process improvements that increase team efficiency.
• Develop automation, scripting, and AI-enabled solutions to improve layout productivity and workflow effectiveness.
• Troubleshoot and resolve layout environment, CAD, and tool-related issues.
• Support layout implementation for high-speed circuit blocks such as SerDes, PLL, DLL, transmitters, receivers, clocking circuits, analog front-end designs, and related PHY circuitry.

Qualifications:

• Bachelor's degree in Electrical Engineering or related technical field, or equivalent industry experience.
• Experience using Cadence Virtuoso or similar custom IC layout tools to develop custom analog, mixed-signal, or ASIC layouts.
• Experience performing physical verification activities including DRC, LVS, ERC, and antenna rule closure.
• Experience working with semiconductor process technologies and applying analog layout fundamentals to optimize circuit performance and manufacturability.

Skills:

• 4+ years of experience in custom analog, mixed-signal, ASIC physical design, or IC layout engineering.
• Master's degree in Electrical Engineering or related technical field.
• Experience with advanced process technologies including FinFET nodes of 16nm or below.
• Experience supporting high-speed analog circuits such as SerDes, PHY, PLL, DLL, TX, RX, clocking circuits, analog front-end designs, or related high-speed blocks.
• Experience with parasitic analysis and extraction tools such as Quantus Insight, ParagonX, or similar technologies.
• Experience developing automation solutions using SKILL, Python, PVL, or related scripting languages, including the use of AI-enabled tools to improve engineering productivity and workflow efficiency.
• Experience with advanced-node layout techniques, including high-speed CMOS and CML layout methodologies.

Work Email

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