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Aeonsemi, founded to tackle advanced analog/mixed-signal challenges, is seeking talented engineers to develop cutting-edge high-speed communication and timing ICs. You must have a proven record in designing complex ICs in state-of-the-art CMOS processes and ship products into volume production.
Responsibilities include architecting and verifying circuits, supervising layout, and supporting product definitions, test programs, and lab characterization. Santa Clara or Portland options.
Founded in October 2018 by technology leaders in mixed signal, DSP, and systems design, Aeonsemi solves complex technical challenges in networking, computing, wireless infrastructure, industrial, and automotive applications with industry leading IC solutions.
We are looking for talented analog/mixed-signal design engineers to develop cutting edge high-speed communication and timing ICs. The candidate must have a proven record of designing complex ICs in state-of-the-art CMOS process technologies and successfully taken products into volume production.
Location can be either:
Santa Clara, California, or Portland, OR