Senior Analog/Mixed-Signal Circuit Designer

Infotree Global Solutions; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Infotree Global Solutions is seeking an experienced analog/mixed-signal IC design engineer in Austin, TX. The role focuses on designing LDOs, charge pumps, voltage detectors, and related PMIC IP, with transistor-level design, verification, and collaboration across teams to ensure robust tapeouts.

Ideal candidates will have deep CMOS device physics knowledge, experience with Cadence Virtuoso/Spectre, and strong problem-solving and communication skills to drive silicon validation and bring-up.

Qualifications

• Strong expertise in analog and mixed-signal circuit design fundamentals.
• Experience with pre-layout and post-layout verification, including stability, noise, PSRR, transient, and corner analyses.
• Experience with silicon bring-up, characterization, debug, and correlation of simulation results with measured silicon data.

Responsibilities

• Design and develop analog/mixed-signal circuits including LDOs, Charge Pumps, Voltage Detectors, and related power management IP.
• Perform transistor-level design, simulation, and optimization across PVT corners to meet performance, power, and reliability requirements.
• Execute pre-layout and post-layout verification, including stability, noise, PSRR, transient, and corner analyses.
• Collaborate with layout, verification, and product engineering teams to ensure successful tapeout and silicon validation.
• Support silicon bring-up, characterization, debug, and correlation of simulation results with measured silicon data.

Skills

Analog/mixed-signal design

Transistor-level design

CMOS device physics

Cadence Virtuoso

Layout collaboration

Problem solving

Communication

Silicon bring-up

Tools

Cadence Virtuoso

Spectre

Job description

Infotree Global Solutions is seeking an experienced analog/mixed-signal IC design engineer in Austin, TX. The role focuses on designing LDOs, charge pumps, voltage detectors, and related PMIC IP, with transistor-level design, verification, and collaboration across teams to ensure robust tapeouts.

Ideal candidates will have deep CMOS device physics knowledge, experience with Cadence Virtuoso/Spectre, and strong problem-solving and communication skills to drive silicon validation and bring-up.