Senior Analog IC Design Engineer Mixed-Signal

LitePoint; Agoura Hills (CA); On-site; USD 119,000 - 191,000; Full time

Job summary

Teradyne’s Semiconductor Test Division in Agoura Hills, CA is seeking a Senior Analog Design Engineer to design low/high-speed circuits for ATE instruments. You will develop specifications, conceive architectures, and perform layout and simulations to optimize performance across process/temperature ranges.

The ideal candidate holds an MSEE with 5+ years or a PhD with 3 years experience in high-frequency, mixed-signal IC design, and has Cadence EDA, Verilog/VHDL skills, and FINFET/BCD exposure.

Qualifications

• MSEE with 5 years of experience or PhD in electrical engineering with 3 years experience in the design and characterization of multiple, high frequency and high scale of integration mixed signal integrated circuits
• Thorough knowledge of high frequency, broad-band Analog Mixed-Signal IC design - both electrical and physical design
• Desire experience in design of VCOs, PLLs, DLLs, ADCs, DACs, clock and data recovery, broadband amplifiers, bias generators, clock distribution networks, high frequency I/Os, high frequency CML designs, high voltage, power circuits
• Solid understanding of CMOS semiconductor device physics and device modeling
• Solid understanding of electromagnetic theory
• Solid understanding of transmission line theory
• Solid understanding of thermal effects of various circuit topologies and different package types
• Involvement in all phases of multiple IC developments from specification to product introduction
• Experience with Cadence Skill or Ocean scripting for automating test benches is a plus
• Proficiency in Verilog or Verilog-A modeling is highly desired
• Direct experience in FINFET desired
• Generic experience in deep sub-micron CMOS (nodes < 65 nm) highly desired
• Experience in BCD technology is a plus
• Experience with high voltage and/or mixed voltage domain circuit design is desired
• Solid understanding and experience with IC characterization at high frequencies using high speed sampling oscilloscopes, spectrum analyzers, VNAs, signal sources
• Solid understanding of working with PDKs
• Experience with ATE test development is a plus
• Ability to work well with a team
• Good communicator

Responsibilities

• Develop detailed circuit specifications for mixed signal circuits
• Conceive circuit architectures and transistor level circuit topologies that satisfy required performance
• Physical implementation (layout) of high speed circuits, either directly or assisting
• Optimization of circuits via simulation (with Cadence EDA tools) over all process and operating conditions
• Integration of circuit elements into large analog/mixed signals ASICs
• Participation in the characterization of ASIC circuits

Skills

High-frequency design

Analog/mixed-signal IC

Transistor-level design

Test and characterization

ATE instrumentation

Education

MSEE with 5+ years

PhD in Electrical Engineering with 3 years

Tools

Cadence EDA tools

Cadence Skill or Ocean scripting

Verilog/Verilog-A modeling

Job description

Teradyne’s Semiconductor Test Division in Agoura Hills, CA is seeking a Senior Analog Design Engineer to design low/high-speed circuits for ATE instruments. You will develop specifications, conceive architectures, and perform layout and simulations to optimize performance across process/temperature ranges.

The ideal candidate holds an MSEE with 5+ years or a PhD with 3 years experience in high-frequency, mixed-signal IC design, and has Cadence EDA, Verilog/VHDL skills, and FINFET/BCD exposure.