Senior Analog Design Architect - DDR I/O & PLL

Talanto; Duluth, Northern (GA, KY); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Renesas is seeking an experienced analog/mixed-signal IC design engineer to architect, verify and optimize CMOS analog blocks for custom ASICs. You will lead DDR I/O interfaces, collaborate with cross-functional teams, and mentor junior engineers while improving power, area and reliability.

The role requires a strong background in high-speed DDR interfaces, signal integrity, and hands-on use of Cadence tools for rigorous verification and validation processes.

Qualifications

• Advanced degree in Electronics/Microelectronics Engineering or related discipline.
• 10–15 years of analog circuit design experience.
• Expertise in high-speed DDR I/O interface design and optimization, including DDR5/DDR6 IO architecture.
• In-depth knowledge of analog Rx/Tx design, including signal integrity and noise immunity.
• Proficiency with analog design tools (Cadence Virtuoso, Maestro, Spectre, HSPICE) and simulation techniques.
• Strong understanding of signal integrity and general analog design principles.

Responsibilities

• Architect, design and verify CMOS analog blocks for custom ASICs to meet performance, area, power and timeline constraints.
• Develop and optimize high-speed DDR I/O interfaces with focus on signal integrity and standards compatibility.
• Collaborate with digital design, verification/test teams and systems engineers for seamless integration.
• Provide technical leadership and mentorship; contribute to design methodologies and best practices.
• Conduct simulations and testing to validate design performance and address issues.

Skills

DDR I/O design

Analog circuit design

Signal integrity

Verbal communication

Education

Advanced degree in Electronics/Microelectronics Engineering

Tools

Cadence Virtuoso

Maestro

Spectre

HSPICE

Job description

Renesas is seeking an experienced analog/mixed-signal IC design engineer to architect, verify and optimize CMOS analog blocks for custom ASICs. You will lead DDR I/O interfaces, collaborate with cross-functional teams, and mentor junior engineers while improving power, area and reliability.

The role requires a strong background in high-speed DDR interfaces, signal integrity, and hands-on use of Cadence tools for rigorous verification and validation processes.