Senior Manager, Analog Eng — Lead Mixed-Signal ASICs

Renesas Electronics; Duluth (GA); Hybrid; USD 185,000 - 225,000; Full time

Job summary

Renesas Electronics is seeking a Senior Manager Analog Engineering in the CMSD division to lead a team of analog designers from concept through product release. You will define specifications, architecture, and IP requirements, coordinating across verification, test, and product engineering to deliver configurable mixed-signal ASICs.

You will mentor your team, drive high-quality development practices, and collaborate with cross-functional groups to optimize performance, power, and die size while

Qualifications

• MSEE with 15+ years in analog and mixed-signal design.
• Excellent communication skills for global collaboration.
• Coaching, mentoring, and development of team members.
• Ability to develop system architectures and lead cross-functional programs.
• Knowledge of AMS simulations and analog modelling.

Responsibilities

• Lead a team of analog designers and act as the technical project lead from concept to market release.
• Develop specifications and architecture with product/marketing to gain competitive advantage.
• Define IP requirements and an integrated development plan for design, verification, and layout.
• Oversee analog/mixed-signal verification plans and ensure quality through peer reviews.
• Collaborate with test, qualification, and product engineering teams; mentor the team.

Skills

Leadership

Mentoring

Communication

System architecture

Cross-functional collaboration

AMS simulations knowledge

Education

MSEE

Job description

Renesas Electronics is seeking a Senior Manager Analog Engineering in the CMSD division to lead a team of analog designers from concept through product release. You will define specifications, architecture, and IP requirements, coordinating across verification, test, and product engineering to deliver configurable mixed-signal ASICs.

You will mentor your team, drive high-quality development practices, and collaborate with cross-functional groups to optimize performance, power, and die size while