Senior AMS Verification Engineer – Analog/Digital SoC Lead

Silicon Labs; United States; Hybrid; USD 140,000 - 190,000; Full time

Benefits offered by this job

Equity rewards (RSUs)

ESPP

Insurance plans with outpatient cover

National Pension Scheme (NPS)

Flexible work policy

Childcare support

Job summary

Silicon Labs is seeking an experienced AMS verification engineer to lead design verification of next-generation IPs/SoCs with emphasis on performance, power, and functionality. You will work across design teams to verify and sign off on verification plans, testbenches, and models, leveraging Verilog, SystemVerilog, and Verilog-AMS.

Responsibilities include leading AMS verification projects, developing testbenches, and ensuring verification closure using Cadence-based flows and SPICE tools.

Qualifications

• Proficient in Verilog, SystemVerilog and Verilog-AMS; strong analog/digital design understanding.
• Experience with AMS verification in mixed-signal SOCs; VLSI testbench development.
• Excellent simulation debugging with waveform analysis and RTL/ schematic review.
• Familiar with Cadence-based flows and SPICE solver tools.
• Unix/Linux environment and scripting in Python/Tcl.

Responsibilities

• Lead AMS verification projects for mixed-signal SOCs or IPs.
• Develop top-level and block-level testbenches and regressions.
• Create and execute test plans, ensure verification closure.
• Collaborate with Design, SoC, Validation, Synthesis & PD teams.
• Extract results, document findings, and present to peers.

Skills

Verilog

SystemVerilog

Verilog-AMS

Analog circuits

Digital design

UVM

Scripting (Python/Tcl)

Education

Bachelor's degree in Electrical and/or Computer Engineering

Master’s degree in Electrical and/or Computer Engineering

Tools

Cadence Virtuoso

SPICE simulators

Unix shell scripting

Job description

Silicon Labs is seeking an experienced AMS verification engineer to lead design verification of next-generation IPs/SoCs with emphasis on performance, power, and functionality. You will work across design teams to verify and sign off on verification plans, testbenches, and models, leveraging Verilog, SystemVerilog, and Verilog-AMS.

Responsibilities include leading AMS verification projects, developing testbenches, and ensuring verification closure using Cadence-based flows and SPICE tools.