Security-Cleared Hardware Design Engineer - FPGA/ASIC

Assertive Professionals

Hanover (MD)

On-site

USD 140,000 - 180,000

Full time

14 days+

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Benefits offered by this job

Sign-on bonus
Relocation stipend
Annual compliance bonus
401k match

Job summary

Assertive Professionals seeks a Hardware Design Engineer to design and test ASIC/FPGA hardware for government-grade projects near Hanover, MD. The role requires extensive IC design and reverse engineering experience, TS/SCI clearance, and Linux-based development skills.

The candidate will lead complex hardware design tasks, develop firmware for DSPs, and collaborate with government customers to meet stringent requirements. Immediate opening with competitive benefits and sign-on bonuses.

Qualifications

  • TS/SCI clearance with ability to pass a Polygraph.
  • 12+ years hardware design engineer experience in IC/microelectronic design or reverse engineering.
  • Familiar with ASIC/FPGA design and verification workflows.
  • Strong experience with Linux-based development environments.

Responsibilities

  • Lead design of ASIC/FPGA components for signal processing applications.
  • Design, test and document IP blocks and hardware modules.
  • Perform reverse engineering on hardware/firmware as required.
  • Coordinate with cross-functional teams to ensure on-time delivery.

Skills

ASIC/FPGA design
VHDL programming
Reverse engineering
Technical leadership

Education

Bachelor's degree in Electrical or Computer Engineering

Tools

Xilinx ISE
Synplify Pro
ModelSim

Job description

Assertive Professionals seeks a Hardware Design Engineer to design and test ASIC/FPGA hardware for government-grade projects near Hanover, MD. The role requires extensive IC design and reverse engineering experience, TS/SCI clearance, and Linux-based development skills.

The candidate will lead complex hardware design tasks, develop firmware for DSPs, and collaborate with government customers to meet stringent requirements. Immediate opening with competitive benefits and sign-on bonuses.

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