RTL2GDS IC Sr. Principal Design Engineer

Cadence; San Jose (CA); On-site; USD 161,000 - 299,000; Full time

Benefits offered by this job

401(k) plan with employer match

Employee stock purchase plan

Medical, dental and vision coverage

Paid vacation and holidays

Job summary

Cadence in California seeks an experienced engineer to drive pre-sales and post-sales activities for Digital IC products. You will solve advanced digital implementation problems, guide customers on tool usage, and deliver technical demos to help meet project schedules.

The role requires hands-on experience with Place & Route, synthesis, and STA tools, with strong scripting skills and excellent communication. Expect a competitive salary and equity as part of the compensation.

Qualifications

• BS/MS/PhD in EE with 10–12 years in design/EDA (digital).
• Deep understanding of ASIC design implementation processes.
• Hands-on experience with Place & Route (Innovus, ICC2, Fusion Compiler).
• Experience with Synthesis (Genus, RTL Compiler, Design Compiler).
• Familiarity with IC digital implementation & signoff STA tools.
• Strong STA and SDC debugging abilities.
• Automation skills using Perl, Tcl and shell scripting.
• Analytical mindset and fast-paced problem solving.
• Excellent customer interaction and presentation skills.

Responsibilities

• Provide technical support to Cadence customers for Digital Design Implementation and Signoff.
• Guide customers to utilize Cadence tools to meet design goals and schedules.
• Conduct technical presentations and product demonstrations.
• Drive technical evaluations and benchmarks to success.
• Collaborate with R&D to enhance tools and methodologies.
• Promote adoption of Cadence tools and technologies.
• Augment flows using Tcl or other programming to meet objectives.
• Capture best practices and lessons learned to improve future engagements.
• Support business case development for process improvement projects.
• Mentor junior engineers.

Skills

Place & Route

Synthesis tools

STA debugging

Perl scripting

Tcl scripting

Shell scripting

Communication skills

Problem solving

Education

Bachelor/Master/PhD in EE

Tools

Innovus

ICC2

Fusion Compiler

Genus

RTL Compiler

Design Compiler

STA tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Job Description

The ideal candidate will be energetic, innovative and enthused with how to help customers, solve their toughest Digital Implementation problems using Cadence technology. Will drive Pre-sales and Post-sales activities at advanced nodes for Cadence Digital IC products.

Key Responsibilities

• Provide technical support to Cadence customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff
• Guide customers on how to best utilize Cadence technologies to achieve their design goals and meet project schedules
• Conduct technical presentations and product demonstrations
• Drive technical evaluations/benchmarks to success
• Work closely with R&D to enhance the tools and methodologies to meet and exceed customer's requirements
• Drive adoption and proliferation of Cadence tools and technologies
• Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows
• Capture best practices and lessons learned from current evaluations/benchmarks and utilize to improve efficiency and success rate in next engagements
• Provide technical support, when developing business case for process improvement projects.
• Provide mentorship to junior engineers

Job Requirements

• Requires a BS or MS or PhD in EE with/or 10-12 years industry related experience in design and EDA (Digital Implementation/Signoff)
• Understands ASIC Design implementation process and steps
• Strong hands-on experience with Place & Route (Innovus, ICC2, Fusion Compiler)
• Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler)
• Experience with EDA tools in the IC digital implementation & signoff flows (STA tools)
• Strong STA and SDC debugging abilities are required.
• Low power analysis, Clock design/analysis and hands-on 7/5nm technology node experience a plus.
• Automation skills using Perl, Tcl and shell scripting essential
• Strong analytical & analysis skills covering digital implementation is critical.
• Proven track record and experience working in a fast paced environment
• Excellent customer interaction & presentation skills

The annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Our benefits programs include:

• paid vacation and paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options
• and more.

We're doing work that matters. Help us solve what others can't.