RTL Power Design Engineer - SoC Efficiency & Innovation

AMD; Austin (TX); On-site; USD 130,000 - 180,000; Full time

Job summary

AMD Austin is seeking an RTL Power Design Specialist to join the Security IP (SECIP) design team. You will define IP-level power specs, drive targets, and optimize power across SoC designs for high performance and efficiency.

Collaborate with SoC power leads, IP design, and verification teams to develop robust power methodologies, measurements, and flows while mentoring junior engineers in a fast-paced, innovative environment.

Qualifications

• Proficiency in Verilog/SystemVerilog and scripting languages such as Python, Tcl, Perl, and Ruby, as well as Makefile-based development environments.

Responsibilities

• Develop and maintain RTL-level IP power specifications and align with SoC power requirements with teams.
• Define, track, and drive IP power targets by correlating design intent with measurements and optimization opportunities.
• Collaborate with verification teams to develop power vectors for simulation-based measurements.
• Partner with static power measurement teams to develop and maintain power regression infrastructure and analyze results.
• Work with corporate power methodology and SoC power teams to adopt advanced power architecture and methods.
• Contribute to corporate power methodology development and influence SoC IP-level power strategy.
• Provide technical leadership in power architecture, design, analysis, and measurement methodology while mentoring team members.

Skills

Technical leadership

Cross-functional collaboration

Mentoring

Problem solving

Education

Bachelor's/Master's/PhD in Electrical Engineering or related field

Tools

Verilog/SystemVerilog

Python

Tcl

Perl

Ruby

Makefile-based environments

Job description

AMD Austin is seeking an RTL Power Design Specialist to join the Security IP (SECIP) design team. You will define IP-level power specs, drive targets, and optimize power across SoC designs for high performance and efficiency.

Collaborate with SoC power leads, IP design, and verification teams to develop robust power methodologies, measurements, and flows while mentoring junior engineers in a fast-paced, innovative environment.