RTL Power Applications Engineer

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

Synopsys, Inc. is seeking an early-career power design engineer to advance RTL power analysis and clock gating techniques. You will work on Prime Power RTL 2.0 flows, support customer evaluations, and contribute to internal documentation and knowledge bases.

You will reproduce issues, document findings with context for senior engineers, and build expertise in low-power design tools while collaborating with sales and field support. This role emphasizes accuracy and clear communication.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field plus 2 years in semiconductor EDA, IC design, or applications/support.
• Working understanding of RTL power concepts including switching power, internal power, leakage power, and clock gating fundamentals.
• Hands-on experience with Linux environments and Tcl scripting for automation or tool interaction.
• Ability to follow established technical flows, reproduce results and document findings clearly for both technical and non-technical audiences.
• Strong written and verbal communication skills.
• Exposure to VCS, Verdi, low-power VLSI coursework, or basic SDC/UPF familiarity is a plus.
• Experience with synthesis tools, waveform debugging, or customer-facing technical support is a plus.

Responsibilities

• Execute Prime Power RTL 2.0 flows for evaluations and internal projects, including library setup, RTL ingestion, SDC/FSDB correlation, synthesis, compute_power runs, and clock gating efficiency reporting.
• Support customers with flow setup, installation troubleshooting, and licensing questions, documenting results and issues for team review and escalation.
• Run RTL power lint checks, summarize findings, and contribute testcase documentation, FAQ entries, and internal knowledge base updates.
• Reproduce customer-reported issues, diagnose routine problems, and escalate complex cases to senior AEs with clear context and supporting data.
• Prepare evaluation collateral and technical summaries using established templates, ensuring accuracy and clarity for both internal teams and customer-facing deliverables.
• Collaborate with sales, field support, and senior applications engineers on assigned accounts, contributing to support cases and evaluation timelines.
• Build working knowledge of Synopsys low-power design tools, RTL power estimation methodologies, and clock gating optimization techniques through hands‑on customer and internal work.

Skills

RTL power concepts

Linux and Tcl scripting

Reproduce results & document

Clear written and verbal communication

Customer-facing support

Synthesis tools & waveform debugging

Issue escalation

Education

Bachelor's degree in Electrical or Computer Engineering or related field

Master's degree with relevant coursework or internship

Tools

Linux

Tcl scripting

VCS

Verdi

SDC/UPF familiarity

Waveform debugging tools

Job description

Synopsys, Inc. is seeking an early-career power design engineer to advance RTL power analysis and clock gating techniques. You will work on Prime Power RTL 2.0 flows, support customer evaluations, and contribute to internal documentation and knowledge bases.

You will reproduce issues, document findings with context for senior engineers, and build expertise in low-power design tools while collaborating with sales and field support. This role emphasizes accuracy and clear communication.