Applications Engineering, Principal Engineer

Synopsys, Inc.; Sunnyvale (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Synopsys, Inc. seeks a senior Applications Engineer focused on RTL power analysis for AI accelerators, mobile processors, and complex SoCs. You will lead engagements, set up full power flows, and calibrate analyses across tools to ensure accurate correlation with signoff data.

You will mentor Staff engineers, drive adoption of Prime Power RTL, and partner with Sales to expand opportunities while influencing R&D on future calibration methods.

Qualifications

• Bachelor's or Master's degree in electrical/computer engineering or related field; PhD preferred for senior role.

Responsibilities

• Lead technical engagements at Tier-1 accounts on RTL power analysis for AI accelerators, mobile processors, and complex SoCs.
• Architect end-to-end power flows spanning clock gating efficiency analysis, physical estimation, and multi-tool integration.
• Drive evaluations that correlate Prime Power RTL with signoff metrics and emulation data.
• Resolve cross-tool escalations involving VCS, Verdi, UPF power intent, and SDF annotations with R&D.
• Coach Staff-level engineers on advanced PPRTL deployments and UPF power verification training.
• Partner with Sales to expand Prime Power RTL footprint and provide feedback to Product teams.
• Engage executive leadership to align power analysis strategy with architecture exploration and pre-implementation signoff.

Skills

RTL power analysis

Clock gating

Glitch power estimation

Memory power modeling

UPF power domain

Prime Power RTL

WCDF calibration

Stimulus quality analysis

PrimeTime PX correlation

VCS simulation

Verdi debugging

SDF back-annotation

Tcl automation

IC design leadership

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Master's degree in related field

Tools

VCS

RTL Architect

Fusion Compiler

PrimeTime PX

ZeBu Emulation

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent a decade building power analysis expertise that goes beyond running tools. You understand that RTL power is not just a metric, it is the decision point that determines whether a mobile SoC ships on time or an AI accelerator meets its thermal budget. You have debugged enough glitch storms, calibrated enough WCDF files, and traced enough UPF violations to know that the methodology is what makes or breaks adoption at a Tier-1 account.

Walking into a customer engagement where the team is stuck between emulation data, PrimeTime signoff numbers, and RTL estimates that do not line up is exactly where you thrive. You ask the right questions about stimulus quality, clock gating efficiency, and NDM correlation before anyone starts blaming the tools. You can sit with an architecture team exploring power budgets for a new AI accelerator and walk out with a calibrated flow they will actually use.

Leading other engineers comes naturally because you have been the person in the room who had to make the call when the data was messy and the schedule was tight. At Synopsys, you will work with customers building the most complex chips in the industry, and what you architect will directly influence how they make power decisions at RTL.

What You'll Be Doing

• Lead technical engagements at Tier-1 accounts on RTL power analysis for AI accelerators, mobile processors, and complex SoCs, serving as the primary advisor on Prime Power RTL 2.0 methodology and multi-tool integration
• Architect end-to-end power flows spanning logical clock gating efficiency analysis, physical glitch estimation with RTL Architect, hybrid NDM import from Fusion Compiler, WCDF calibration against PrimeTime PX, and FSDB stimulus quality validation
• Drive complex evaluations that demonstrate correlation between Prime Power RTL, PrimeTime PX signoff metrics, and ZeBu Empower emulation-based power data, defining calibration strategy when customer data is ambiguous or incomplete
• Resolve cross-tool escalations involving VCS simulation, Verdi debug, UPF multi-rail domains, and SDF back-annotation, working directly with R&D when root cause spans product boundaries
• Coach and review the work of Staff-level Applications Engineers on advanced PPRTL deployments, deliver technical training on CGE/CGR/DACGE analysis and UPF power intent verification
• Partner with Sales on strategic opportunities to expand Prime Power RTL footprint, lead benchmark engagements that influence competitive decisions, and provide structured feedback to R&D and Product Marketing on customer methodology gaps
• Engage executive leadership at customer accounts to align power analysis strategy with their architecture exploration and pre-implementation signoff objectives

The Impact You Will Have

• Enable Tier-1 customers to make architecture and power budget decisions at RTL with confidence, reducing costly late-stage surprises in physical implementation and signoff
• Drive measurable Prime Power RTL license expansion and adoption across AI, mobile, and datacenter SoC segments through successful benchmark wins and methodology validation
• Improve correlation accuracy between RTL power estimates and PrimeTime PX signoff by defining and deploying calibration best practices that become repeatable across accountsAccelerate Staff-level AE capability on advanced PPRTL flows, reducing time-to-resolution on complex customer engagements and improving team technical depth
• Influence Prime Power RTL product roadmap and cross-tool integration priorities by delivering structured R&D feedback grounded in real customer deployment challenges
• Strengthen Synopsys' technical credibility with executive engineering leadership at strategic accounts, positioning the company as the authority on RTL-stage power methodology
• Reduce customer evaluation and deployment timelines by architecting flows that integrate cleanly with existing VCS, Verdi, RTL Architect, and Fusion Compiler environments

What You'll Need

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 10+ years in EDA applications engineering, design consulting, or IC design, or Master's degree with 8+ years (PhD preferred)
• Expert-level knowledge of RTL power analysis including clock gating efficiency (CGE/CGR/DACGE), glitch power estimation, memory power modeling, and multi-rail UPF power domain analysis
• Deep hands-on experience with Prime Power RTL, including flow setup, WCDF calibration, stimulus quality analysis, and correlation methodology
• Advanced proficiency with VCS simulation, Verdi debug, SDF back-annotation, UPF power intent, and Tcl-based flow development for automated deployment
• Proven track record leading complex customer engagements at strategic accounts with measurable business impact such as license expansion, benchmark wins, or methodology adoption
• Experience with PrimeTime PX signoff correlation, RTL Architect or Fusion Compiler physical estimation flows, or ZeBu emulation-based power analysis is a strong plus
• Familiarity with VC SpyGlass or VC LP low-power verification tools and IEEE 1801 UPF specification is a plus

Who You Are

• You can walk into a customer meeting where RTL power numbers do not match emulation data or signoff results, ask three diagnostic questions about stimulus coverage and clock gating assumptions, and identify the root cause before the hour is up
• Leading a multi-week evaluation across PPRTL, VCS, RTL Architect, and PrimeTime PX does not overwhelm you because you know how to structure the work, set clear milestones, and keep both the customer and internal teams aligned
• When a Staff AE brings you a tricky UPF multi-rail scenario or a glitch correlation issue, you do not just solve it, you walk them through the reasoning so they can handle the next one independently
• You push back when a customer asks for a flow that will not scale or when an internal team wants to commit to a timeline that skips necessary calibration steps, and you do it in a way that builds trust rather than friction
• Translating a complex WCDF calibration strategy or NDM import methodology into a clear technical presentation for a VP of Engineering is something you have done enough times that it feels natural
• You stay current on RTL power challenges in AI accelerators, mobile SoCs, and datacenter designs because you are genuinely curious about how architecture decisions at RTL ripple through the entire design cycle

The Team You'll Be Part Of

You will join Synopsys' Applications Engineering organization supporting the low-power design portfolio, working closely with Sales, R&D, and Product Marketing teams to drive Prime Power RTL adoption at strategic accounts. Your work will span customer-facing technical leadership, cross-functional methodology development, and mentorship of Staff-level engineers across North America.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.