Applications Engineering

Synopsys, Inc.; Northern (KY); Hybrid; USD 120,000 - 160,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced Applications Engineer to lead Prime Power RTL 2.0 deployments from scoping to go-live. You will deploy, tune, and validate flows across CGE, RTLA, and multi-rail UPF contexts, guiding customers toward production-ready signoff readiness.

You will mentor junior engineers, develop Tcl automation, and collaborate with R&D, sales, and customer teams to scale RTL power analysis in production environments.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years in EDA applications, IC design, or low-power methodology; or a Master's with 3+ years.
• Hands-on experience deploying RTL power analysis tools in customer or production environments.
• Working knowledge of CGE, glitch analysis, and memory power modeling.
• Proficiency with VCS, Verdi, FSDB waveform formats, SDC constraint flows, and Tcl scripting for EDA tool automation.
• Demonstrated ability to independently manage customer-facing technical projects from kickoff through delivery.
• Experience with Prime Power RTL 2.0, RTL Architect, Fusion Compiler, or NDM-based design flows is a strong plus.
• Familiarity with PrimeTime PX signoff correlation, UPF/IEEE 1801 multi-rail analysis, or SoC and AI accelerator design methodologies is a strong plus.
• Prior Applications Engineering role at an EDA vendor or customer-facing technical role is a strong plus.

Responsibilities

• Lead Prime Power RTL 2.0 evaluations and production deployments from scoping through go-live.
• Deploy and tune logical flows using CGE, lint, and ODC; physical flows with RTLA and glitch/SDF integration.
• Apply WCDF-based calibration and synthesize with apply_calib to improve RTL-to-signoff correlation.
• Independently troubleshoot elaboration failures, library mismatches, SDC constraints, FSDB parsing, and multi-rail UPF issues.
• Present flow options, CGE/CGR/DACGE results, and deployment timelines to customer teams.
• Develop Tcl-based automation for staged save/restore methodologies and flow integration.
• Mentor Level 1 and Level 2 Applications Engineers; contribute to internal playbooks.

Skills

RTL power analysis

CGE troubleshooting

FSDB knowledge

Tcl scripting

VCS/Verdi

UPF multi-rail

SoC accelerators

NDM design flows

customer-facing projects

Prime Power RTL 2.0

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree (3+ years)

Tools

CGE

lint

ODC

RTLA

RTL Architect

Fusion Compiler

PrimeTime

Job description

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years in the space where power analysis stops being theoretical and starts being the thing that makes or breaks a tape-out schedule. You know that RTL power is not just about running a tool, it is about understanding why the numbers look wrong, where the FSDB stimulus is lying to you, and how to get a customer's flow from 'interesting evaluation' to 'this is now in our production signoff checklist.'

You are the engineer who can walk into a customer meeting, listen to their design constraints and flow pain points, then sketch out a deployment plan that accounts for their NDM import mess, their multi-rail UPF complexity, and the fact that their verification team has never heard of CGE. You do not wait for perfect data. You work with what you have, ask the right questions, and build a path forward that actually works in their environment, not just in a demo deck.

Debugging is where you thrive. Elaboration failures, glitch correlation mismatches, SDF timing issues that make no sense until you dig three layers deeper, that is your comfort zone. You have learned that the best customer engagements are the ones where you teach someone how to solve the next problem themselves, not just fix the one in front of you today.

At Synopsys, you will own Prime Power RTL 2.0 deployments end to end for real customers building real chips, and the flow you deliver this quarter will still be running two years from now.

What You'll Be Doing

• Lead Prime Power RTL 2.0 evaluations and production deployments from scoping through go-live, including methodology selection, flow customization, and customer knowledge transfer
• Deploy and tune logical flows using CGE, lint, and ODC, physical flows with RTLA and glitch/SDF integration, and hybrid NDM import flows across customer design environments
• Apply WCDF-based calibration and synthesize with apply_calib to improve RTL-to-signoff correlation when designs demand tighter accuracy, and guide customers on FSDB stimulus quality and coverage
• Independently troubleshoot elaboration failures, library mismatches, SDC constraints, FSDB parsing issues, multi-rail UPF problems, and power accuracy gaps across VCS, Verdi, PrimeTime, and RTL Architect
• Present flow options, CGE/CGR/DACGE results, and deployment timelines to customer engineering teams and manage project deliverables through completion
• Develop Tcl-based automation for staged save/restore methodologies, custom reporting, and flow integration that fits into customer regression environments
• Mentor Level 1 and Level 2 Applications Engineers, contribute to internal playbooks and best practices, and provide R&D feedback based on field deployment patterns

The Impact You Will Have

• Accelerate customer adoption of RTL power analysis by delivering deployments that integrate cleanly into existing signoff flows and reduce time-to-results by weeks
• Improve power accuracy and correlation for SoC and AI accelerator designs, enabling customers to make better architectural and implementation decisions earlier in the design cycle
• Reduce customer escalations and support load by building flows that are robust, repeatable, and documented well enough that design teams can run them independently
• Influence Prime Power RTL 2.0 product direction by surfacing real deployment blockers, flow gaps, and feature requests directly from customer engagements
• Expand Synopsys footprint in accounts by proving that RTL power analysis is not just a nice-to-have but a production-ready part of the low-power design methodology
• Build internal AE capability by mentoring junior engineers and creating reusable deployment assets that shorten ramp time on future customer engagements
• Strengthen customer relationships by becoming the engineer they call first when something breaks, because you have already solved the hard problems in their environment

What You'll Need

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 5+ years in EDA applications, IC design, or low-power methodology, or Master's degree with 3+ years
• Hands-on experience deploying RTL power analysis tools in customer or production environments, with working knowledge of CGE, glitch analysis, and memory power modeling
• Proficiency with VCS, Verdi, FSDB waveform formats, SDC constraint flows, and Tcl scripting for EDA tool automation
• Demonstrated ability to independently manage customer-facing technical projects from kickoff through delivery, including timeline management and stakeholder communication
• Experience with Prime Power RTL 2.0, RTL Architect, Fusion Compiler, or NDM-based design flows is a strong plus
• Familiarity with PrimeTime PX signoff correlation, UPF/IEEE 1801 multi-rail analysis, or SoC and AI accelerator design methodologies is a strong plus
• Prior Applications Engineering role at an EDA vendor or customer-facing technical role at a semiconductor company is a strong plus

Who You Are

• You can walk into a customer meeting where the flow is broken, the timeline is tight, and the data is incomplete, and you leave with a clear plan that the customer actually believes in
• Debugging energizes you more than it frustrates you, whether it is a UPF multi-rail issue that makes no sense or an FSDB stimulus problem that is masking real power behavior
• You know how to explain a calibration tradeoff or a glitch correlation gap to a design lead in two sentences without losing the technical nuance or oversimplifying the fix
• You are comfortable saying 'I do not know yet, but here is how I will figure it out' and then actually figuring it out without needing someone to hold your hand
• You have learned that the best customer engagements end with the customer being able to run the flow themselves, not with them depending on you to run it for them every time
• You can manage three customer deployments at once, keep the timelines straight, and still find time to help a junior AE who is stuck on an elaboration issue

The Team You'll Be Part Of

You will join the Applications Engineering organization supporting Prime Power RTL 2.0 and low-power design methodology across Synopsys customer accounts. The team works closely with R&D, sales, and customer design teams to deploy, tune, and scale RTL power analysis in production environments. Your work will directly shape how customers adopt and integrate power analysis into their signoff flows, and you will collaborate with AEs across logical, physical, and signoff domains to deliver complete low-power solutions.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.