RTL Optimization CAD Engineer – Graph ML & Equity

NVIDIA Corporation; Santa Clara (CA); Hybrid; USD 136,000 - 219,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation in Santa Clara, CA seeks a CAD Software Engineer focusing on RTL quality, timing, and power optimization. You’ll work on graph-based RTL traversal, leverage AI/ML ideas, and collaborate with RTL designers to improve data path latency and power delivery across SOC designs.

Ideal candidates have strong C++ with graph algorithms, RTL knowledge, and exposure to EDA toolchains. Hybrid work and deep freedom are emphasized at NVIDIA.

Qualifications

• MS or PhD in Electrical Engineering or Computer Science or equivalent experience.
• 3+ years of CAD software and VLSI hardware design experience.
• Strong C++ development focus on graph traversal, pattern matching, and optimization.
• Familiarity with RTL design, Verilog/SystemVerilog, and hardware design concerns.

Responsibilities

• Invent parallel, graph-based RTL traversal, analysis, and manipulation methods.
• Assess RTL changes impact on latency, power, DFT, clocking, and power delivery.
• Explore ML/AI techniques to suggest or implement RTL modifications.
• Contribute to high performance software design including multithreading and memory efficiency.

Skills

C++

Graph algorithms

RTL design

Verilog/SystemVerilog

EDA tools

Communication

CAD software

Education

MS or PhD in Electrical Engineering or Computer Science

Tools

Verific

Espresso

Job description

NVIDIA Corporation in Santa Clara, CA seeks a CAD Software Engineer focusing on RTL quality, timing, and power optimization. You’ll work on graph-based RTL traversal, leverage AI/ML ideas, and collaborate with RTL designers to improve data path latency and power delivery across SOC designs.

Ideal candidates have strong C++ with graph algorithms, RTL knowledge, and exposure to EDA toolchains. Hybrid work and deep freedom are emphasized at NVIDIA.