RTL Design Engineer

The Consensus; San Jose (CA); On-site; USD 140,000 - 180,000; Full time

Benefits offered by this job

Medical, dental & vision

Housing subsidy

Relocation support

Wellness benefits

Daily meals

Unlimited compute budget

Job summary

Etched seeks an experienced RTL Engineer to ensure AI chips operate correctly and efficiently. You will develop verification strategies for ASIC designs and work on state-of-the-art ML architectures. The role offers a fast-paced, autonomous environment with meaningful impact on chip performance.

You will contribute to projects like implementing floating point math blocks and optimizing timing and area. A strong background in RTL and verification, plus a willingness to learn transformer concepts,

Qualifications

• At least 5 years of work experience in RTL development.
• Experience with high-speed digital logic.
• Proficiency in standard RTL design and synthesis tools.
• Familiarity with verification work and writing test benches.

Responsibilities

• Develop and implement design verification strategies for RTL ASIC designs.
• Implement a block to efficiently compute floating point math operators.
• Provide feedback to the uArch team to meet timing and area constraints.

Skills

High-speed digital logic

RTL development

Verification concepts

Willingness to learn AI transformers

Tools

Verilog

SystemVerilog

VHDL

EDA tools

Python

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both our existing and upcoming ASIC designs.

In this role, you will work closely with state-of-the‑art architectures for machine learning. You do not need to have experience working with these yet, but you will be willing and able to learn quickly. You will work in a fast‑paced environment with a high degree of autonomy, and be responsible for a key part of Etched’s success.

Representative projects

• Implement a block to efficiently compute floating point math operators
• Provide feedback to the uArch team to make sure blocks meet timing and area constraints

You may be a good fit if you

• At least 5 years of work experience in RTL development.
• Experience with high‑speed digital logic.
• Proficiency in standard RTL design and synthesis tools
• Familiarity with verification work and writing test benches
• Are able to learn quickly about transformers and other aspects of modern artificial intelligence
• Willing to start quickly

Strong candidates may also have experience with (Nice‑to‑have qualifications)

• Experience with PCIe, Ethernet, or HBM technologies
• Familiarity with modern ML and LLM model architectures.
• Familiarity with numerical representations and functions
• Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Benefits

• Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
• Housing subsidy of $2k per month for those living within walking distance of the office
• Relocation support for those moving to San Jose (Santana Row)
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office
• Unlimited compute budget subject to ROI justification

How we’re different:

Etched believes in the Bitter Lesson. We are the first inference‑focused frontier AI system, betting early on transformer and transformer‑like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in‑person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.