RTL Design Engineer

Mirafra Technology; San Diego (CA); On-site; USD 100,000 - 130,000; Full time

Job summary

Mirafra Technology is seeking a Design and Verification Engineer located in San Diego, California. Candidates should have a minimum of 5 years of experience in design and verification, including micro architecture and RTL design.

Key skills include timing closure, SystemVerilog/Verilog, and communication skills for collaboration across teams. The role focuses on high-speed custom building blocks.

Qualifications

• Minimum 5 years of experience in design and verification.
• Experience with micro architecture, RTL design, and test planning.
• Excellent documentation skills and ability to work across multiple teams.

Skills

Design and verification experience including micro architecture, RTL design and test planning

Timing closure experience including timing constraints and PTSI

Prior experience in digital and mixed signal circuit design for high speed PHYs

Hands-on experience with SystemVerilog/Verilog, DFT insertion, and timing closure

Hands-on experience with HVLs and Testbench architectures

Exposure to high speed custom building blocks

Excellent communication skills

Job description

About Mirafra : Mirafra is a software service‑based organization started in 2004.

We are 500+ employees in India and 250+ in the US. Clear visibility to senior management helps for constant professional growth.

Job Description

Minimum 5 years of experience with the following skills.

• Design and verification experience including micro architecture, RTL design and test planning
• Timing closure experience including timing constraints and PTSI
• Prior experience in digital and mixed signal circuit design for high speed PHYs
• Hands‑on experience with SystemVerilog/Verilog, DFT insertion, and timing closure
• Hands‑on experience with HVLs and Testbench architectures
• Exposure to high speed custom building blocks, such as IOs, PLLs, DLLs, LDOs, etc.
• Excellent communication skills, including documentation and the ability to work across multiple teams in multiple locations

Qualifications

Minimum 5 years of experience with the following skills.

• Design and verification experience including micro architecture, RTL design and test planning
• Timing closure experience including timing constraints and PTSI
• Prior experience in digital and mixed signal circuit design for high speed PHYs
• Hands‑on experience with SystemVerilog/Verilog, DFT insertion, and timing closure
• Hands‑on experience with HVLs and Testbench architectures
• Exposure to high speed custom building blocks, such as IOs, PLLs, DLLs, LDOs, etc.
• Excellent communication skills, including documentation and the ability to work across multiple teams in multiple locations

Additional Information

• Experience with LPDDR3/LPDDR4 protocols
• Experience in low power implementation techniques
• Experience in architecture, RTL design for high speed datapaths, linting, synthesis, STA, and DFT
• Experience in advanced digital CMOS processes

All your information will be kept confidential according to EEO guidelines.