RTL DESIGN ENGINEER

Semiconductor Engineering; North Reading (MA); On-site; USD 120,000 - 190,000; Full time

Job summary

Teradyne's Silicon Technology Engineering (STE), Digital ASIC Group is seeking an RTL Designer to develop next-generation large mixed-signal ASICs for SOCs and memory test instruments. You will work with an analog team and product architects across specification, architecture, design, verification, and silicon bringup, using cutting-edge AI tools to boost productivity.

Responsibilities include RTL design of mission-critical blocks, IP integration, collaborating with verification on test plans

Responsibilities

• RTL design of mission-critical blocks in collaboration with chip architect
• Integration of industry standard and Teradyne IPs
• Collaborating with the verification team on test plans, debug support and coverage closure

Job description

Teradyne’s Silicon Technology Engineering (STE), Digital ASIC Group is responsible for developing advanced node ASICs for Teradyne next generation products such as SOC and Memory Test Instruments. Teradyne’s products in many ways must be ahead of the semiconductor industry in order for our customers to ship production chips/products. You will join a best-in-class Digital team as a RTL Designer working in collaboration with an Analog team and product architects to develop Teradyne’s next generation large Mixed Signal ASICs. You will be involved in all phases of development including specification, architecture, design, verification, physical design, and silicon bringup, and will have cutting-edge AI tools available to optimize your productivity.

Responsibilities

• Developing specifications, micro-architecture, and RTL design of mission critical blocks in collaboration with the chip architect
• Integration of industry standard and Teradyne custom IPs
• Collaborating with the verification team on test plans, debug support and coverage closure to ensure high quality RTL and first pass silicon success
• Providing timing constraints and STA support to the Physical Design team through timing closure
• Providing post silicon lab bringup and debug support