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Join a forward-thinking company as an RTL Design Engineer, where you'll play a pivotal role in the development of cutting-edge AI chips. This innovative firm is focused on creating model-specific hardware that revolutionizes the AI landscape. You will be responsible for ensuring the efficiency and correctness of ASIC designs while collaborating with a talented team. The role offers a unique opportunity to work in a fast-paced environment, contributing to projects that push the boundaries of technology. If you're eager to learn and thrive in a dynamic setting, this position is perfect for you.
About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning.
RTL Design Engineer
As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both our existing and upcoming ASIC designs.
In this role, you will work closely with state-of-the-art architectures for machine learning. You do not need to have experience working with these yet, but you will be willing and able to learn quickly. You will work in a fast-paced environment with a high degree of autonomy, and be responsible for a key part of Etched’s success.
Representative projects:
You may be a good fit if you:
Strong candidates may also have experience with:
We encourage you to apply even if you do not believe you meet every single qualification.
How we’re different:
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Benefits: