Memory PHY RTL Design Engineer

Advanced Micro Devices, Inc.; California, Santa Clara (MO, CA); On-site; USD 80,000 - 120,000; Full time

Job summary

Join a forward-thinking company as a Design Engineer in the Memory PHY team, where your expertise in RTL and firmware development will contribute to cutting-edge memory technologies. This role involves designing high-speed LPDDR and DDR IPs, collaborating with talented engineers across various locations, and enhancing methodologies for industry-leading products. If you're passionate about digital design and eager to tackle complex challenges in a dynamic environment, this opportunity is perfect for you. Be part of a team that drives innovation and transforms lives with advanced technology.

Benefits

Health insurance

401(k) plan

Paid time off

Flexible working hours

Professional development opportunities

Qualifications

• Experience in digital design and verification.
• Proficient in Verilog and System Verilog.
• Strong analytical and problem-solving skills.

Responsibilities

• Design and implement RTL for memory I/O.
• Collaborate with architects and engineers on new features.
• Debug design failures and resolve issues.

Skills

Digital design engineering

Verilog

System Verilog

C

C++

Python

Perl

TCL

Timing closure

Debugging firmware and RTL code

Education

Bachelors in Computer Engineering

Masters in Electrical Engineering

Tools

Simulation tools

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

THE ROLE:

The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and Firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry-leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• RTL design for memory I/O
• PHY Digital Architecture development from pathfinding, coding, verification to physical implementation
• PHY link layer design, implementation & verification with Analog and System architect.
• PHY Analog/Digital co-design
• Digital design and RTL coding
• Timing Synthesis & Drive Physical implementation
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the unit tests
• Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues

PREFERRED EXPERIENCE:

• Digital design engineering experience
• Experienced with Verilog, System Verilog, C, and C++
• Excellent knowledge of Verilog, System Verilog and a scripting language; experience with Python, Perl and TCL is a plus
• Knowledge of clocking architectures, synchronization, and CDC methodology
• Experience with synthesis, Timing closure
• SERDES, DDR, Memory Controller, or MAC Design experience is preferred
• Proficient in debugging firmware and RTL code using simulation tools
• Strong understanding of computer organization/architecture.
• Mixed signal RTL, Low power design experience is a plus
• Exposure to leadership or mentorship is an asset

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: Santa Clara, Boxborough

#LI-TB2

Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.