RTL/ASIC Design Engineer I — Shape Next-Gen SoCs

Microchip Technology Inc.; Pennsylvania; On-site; USD 95,000 - 140,000; Full time

Job summary

Microchip Technology Inc. is seeking a skilled engineer to design RTL blocks for an SOC with diverse IP cores and high-speed interfaces.

Responsibilities include RTL design, synthesis, timing verification, and collaboration with FPGA and test teams. Requires 0–2.5 years in RTL design, a relevant bachelor’s degree, SystemVerilog proficiency, and Linux scripting. Up to 25% travel may be required.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or Computer Science.
• Knowledge of high-speed RTL design and verification.
• Experience with SystemVerilog and RTL simulation.
• Ability to write detailed design specifications.
• Proficiency in Linux scripting and debugging.

Responsibilities

• General RTL and ASIC development.
• Detailed module design, performance analysis and detailed design specification creation.
• Participate in the RTL implementation, synthesis, simulation, pre-layout/post-layout timing verification.
• Understanding of high-speed design techniques to improve bandwidth and reduce latency.
• Support porting the design into test chips and emulation platforms; FPGA tools knowledge is advantageous.

Skills

RTL Design

ASIC

SystemVerilog

FPGA

Linux

Scripting

Education

Bachelor’s in Electrical Engineering or Computer Engineering or Computer Science

Master’s in Electrical Engineering or Computer Engineering or Computer Science

Tools

RTL design tools

Job description

Microchip Technology Inc. is seeking a skilled engineer to design RTL blocks for an SOC with diverse IP cores and high-speed interfaces.

Responsibilities include RTL design, synthesis, timing verification, and collaboration with FPGA and test teams. Requires 0–2.5 years in RTL design, a relevant bachelor’s degree, SystemVerilog proficiency, and Linux scripting. Up to 25% travel may be required.