Sr. Staff Engineer, RTL Physical Implementation Lead

Tenstorrent; Jackson (TN); Hybrid; USD 100.000 - 500.000; Vollzeit

Zusammenfassung

Tenstorrent is seeking an engineer to join the CPU design team and lead the front-end RTL physical implementation, driving CAD flows and refining core configurations for high performance RISC-V CPUs. You will work with DV, PD, RTL and performance teams to ensure functional timing and power-converged designs.

This hybrid role is based in the United States, with options in Austin, TX or Santa Clara, CA, and the company welcomes candidates at various experience levels during the interview process.

Qualifikationen

• Expert in front-end physical design optimizing PPA.
• Proficient RTL coding in Verilog/VHDL with simulation experience.
• Background in CPU micro-architecture and flow integration.

Aufgaben

• Own front-end physical implementation and PPA definition.
• Collaborate with microarchitects and RTL to optimize frequency, power, and area.
• Define floorplans and early area/power/frequency estimates.
• Bridge PD and design teams to standardize workflows.
• Communicate PPA trade-offs to RISC-V and PD teams.
• Drive innovative PD techniques and report results.

Kenntnisse

RTL coding Verilog/VHDL

Front-end physical design

PPA optimization

Synthesis, place & route

CPU micro-architecture

Tools

Synthesis tools

Place & Route tools

Power analysis tools

RTL simulators

Jobbeschreibung

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a talented engineer to join our CPU design team and lead the front-end RTL physical implementation team. Drive CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design.

This role ishybrid, based out of Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• An expert in physical design practices used to optimize PPA
• Experienced in high-performance physical design.
• Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis.
• Skilled in synthesis, place and route tools including flows and physical design methodology.
• Background in CPU micro-architecture.

What We Need

• Own front‑end physical implementation and PPA definition for a high‑performance RISC‑V CPU and CPU subsystem
• Work closely with microarchitects and RTL designers to “make the IP better” by optimizing frequency, power, and area across process nodes
• Define initial floorplans and early area, power, and frequency estimates for key CPU and subsystem configurations
• Partner with the broader PD organization and PD leads to improve and standardize methodologies, flows, and customer collateral for CPU, subsystem, and system IPs, acting as a “PD for IP” specialist bridging PD and design teams
• Use innovative techniques to optimize power, performance, and area while driving physical design experiments and evaluating results.
• Summarize and communicate PPA trade‑offs and recommendations to the broader RISC‑V and PD teams

What You Will Learn

• Develop and lead a high performance physical design team tailored to solving difficult and unique problems to generate leading IP solutions
• End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
• Hands-on experience optimizing CPU designs and driving PPA improvement.
• Integration of open-source and industry-standard tools to improve physical flows and results.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

• Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.